Backside Power Rail Fin Corners for Source/Drain Etch Protection
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Solution Overview
Problem
As semiconductor device size shrinks, forming metal power rails and signal lines becomes challenging due to limited space, and the etching process for backside semiconductor removal poses a risk to source/drain features, particularly for n-type devices, requiring high precision and protection during backside contact formation.
Innovation Solution
The method involves forming a convex surface on the source/drain features by maintaining a corner portion during backside semiconductor removal, using a low etching rate process to create a triangular profile with a crystal facet, and employing a thick buffer layer to protect these features, allowing for precise recess formation and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the etching process is used for backside semiconductor removal, then the backside contact formation is enabled, but the source/drain features are at risk of being damaged due to low etching selectivity
Solution Approach 1:
A buffer layer is formed over the source/drain features before the etching process. This buffer layer serves as a protective barrier that is deposited in advance to prevent etchant from directly contacting and damaging the source/drain features during backside semiconductor removal
Solution Approach 2:
The buffer layer acts as an intermediary between the etchant and the source/drain features. It provides etch selectivity by being more resistant to the etchant than the source/drain features, allowing the etching process to proceed on the backside semiconductor while protecting the underlying sensitive structures
2Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated, but the metal layer routing becomes more complex and space for power rails is limited
Solution Approach 1:
Power rails and contacts are formed on the backside of the semiconductor device instead of only on the front side. This utilizes the third dimension (depth/backside) to accommodate power distribution, thereby reducing the space requirements and complexity on the front-side metal layers while maintaining high integration density
3Productivity
If a high etching rate process is used for backside semiconductor removal, then the processing time is reduced, but the precision for source/drain feature protection is compromised
Solution Approach 1:
The buffer layer is deposited before the etching process to provide a protective barrier. This preliminary action allows the use of faster etching rates while maintaining precision, as the buffer layer absorbs the variability in etch rate and provides a consistent protection layer
Solution Approach 2:
The etch selectivity between the buffer layer and the source/drain features is optimized by adjusting buffer layer composition and thickness parameters. This allows for faster etching rates while maintaining sufficient protection, as the buffer layer parameters are tuned to provide adequate margin against etch rate variations
Data Source
AI summary
Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.