Backside Power Rail Layout With CPODE Power Taps
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Solution Overview
Problem
As integrated circuits scale down, power rails on the frontside of semiconductor devices lead to increased voltage drop and power consumption, and existing methods for forming power rails on both the frontside and backside of integrated circuits have not been entirely satisfactory in addressing these issues.
Innovation Solution
The implementation of a continuous-poly-on-diffusion-edge (CPODE) process to form conductive power taps between frontside and backside power rails, using existing device features as power taps without increasing layout area or routing complexity, and enhancing device performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If power rails are scaled down with integrated circuits, then device scaling is achieved, but voltage drop across power rails increases
Solution Approach 1:
The patent introduces backside power rails as a third-dimensional solution to the traditional planar power distribution network. By extending power delivery to the backside of the substrate, the invention creates a three-dimensional power rail architecture that reduces current path length and resistance without increasing lateral device dimensions, thereby reducing voltage drop while maintaining scaled device footprints.
Solution Approach 2:
The power distribution network is segmented into frontside and backside power rails, allowing independent optimization of each segment. This segmentation enables shorter current paths by allowing power to be delivered from both sides of the substrate, reducing the overall resistance and voltage drop in the power delivery network.
2Device complexity
If power rails are placed only on top of transistors, then routing is simplified, but power consumption increases
Solution Approach 1:
By moving power rails to the backside of the substrate, the invention utilizes the third dimension (vertical space) to reduce power consumption. This allows power to be delivered closer to the transistor power contacts without increasing lateral routing complexity, as the backside power rails can be positioned directly beneath the transistor power diffusion regions.
Solution Approach 2:
The backside power rails act as an intermediary power delivery path between the power supply and the transistor power contacts. This intermediary structure reduces the resistance in the power delivery path, thereby reducing power consumption while maintaining the simplicity of the routing architecture.
3Loss of energy
If backside power rails are added to reduce voltage drop, then power delivery is improved, but manufacturing complexity increases
Solution Approach 1:
The backside power rail structure is formed during the early stages of the fabrication process, before the frontside transistor structures are completed. This preliminary formation of the backside power rails allows them to be integrated into the overall device structure without requiring additional processing steps, thereby reducing manufacturing complexity despite the added functionality.
Solution Approach 2:
The invention merges the backside power rail formation with existing fabrication processes by utilizing the same deposition and etching steps that form other device structures. This consolidation of processes reduces the overall manufacturing complexity by combining multiple functions into unified process steps.
Data Source
AI summary
A semiconductor structure includes a first gate structure extending lengthwise along a first direction, a second gate structure extending lengthwise along the first direction and aligned with the first gate structure, a first gate cut feature abutting the first gate structure, a second gate cut feature abutting the second gate structure, and a conductive feature disposed between the first and second gate cut feature. A bottom surface of the conductive feature is below bottom surfaces of the first and second gate cut features.