Backside Power Rail Formation Using Sacrificial Via Fill
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Solution Overview
Problem
Traditional semiconductor transistor architectures require larger areas due to the integration of power rails and signal lines, leading to increased complexity and reduced transistor density.
Innovation Solution
The method involves forming a sacrificial fill material using an anisotropic dry etch process and selective epitaxial growth, which allows for the creation of backside power rail structures without increasing transistor area, enabling self-aligned epitaxial source/drain structures and simplified transistor formation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional front side power grid or backside power sources with vias are used, then power supply to transistors is achieved, but transistor area increases and transistor density decreases
Solution Approach 1:
The patent moves the power rail formation from the front side (planar dimension) to the backside of the substrate (third dimension), allowing power delivery without occupying additional transistor area on the active device plane
Solution Approach 2:
The method performs preliminary actions by forming the opening and depositing oxide layers before transistor fabrication is complete, and uses a sacrificial material that is removed after source/drain epitaxial growth, allowing power rail formation to be integrated into the transistor fabrication sequence without interfering with device formation
2Manufacturing precision
If anisotropic dry etch process is used to remove oxide layer, then selective removal from bottom portion of opening is achieved, but process complexity increases
Solution Approach 1:
The patent applies local quality by creating different oxide layer configurations in different locations - a conformal oxide layer on the sidewalls that remains as a spacer, and oxide at the bottom that is selectively removed, achieving spatially differentiated material properties through the etch process
Solution Approach 2:
The partial oxide spacer acts as an intermediary that defines the etch stop and controls the depth of opening formation, allowing precise control of the opening depth without requiring complex real-time process control
3Manufacturing precision
If selective epitaxial growth is used to grow sacrificial fill material, then bottom-up fill is achieved, but process parameters must be precisely controlled
Solution Approach 1:
The patent exploits parameter changes by varying the hydrogen chloride gas flow rate (60-90 sccm) and chamber pressure (1-100 Torr) to control the epitaxial growth rate and selectivity, achieving bottom-up fill of the opening while maintaining control over the growth characteristics
Solution Approach 2:
The process utilizes phase transitions in the gas phase during epitaxial growth, where hydrogen chloride gas reacts with silicon to deposit solid silicon material, leveraging the gas-to-solid phase change for controlled material deposition
4Productivity
If integrated cluster tool without air break is used, then process continuity is improved, but contamination risk increases
Solution Approach 1:
The patent maintains an inert vacuum environment throughout the integrated cluster tool process sequence, eliminating air breaks that would introduce oxygen and water vapor contamination, thereby achieving both process continuity and contamination prevention through sustained vacuum conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces transistor area requirements, increases transistor density, and simplifies the formation processes by eliminating the need for post-etch wet clean processes and preventing pinch-off voids and selectivity loss.
Implementation Method 1
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas that removes the oxide layer from a field of the substrate and only from a bottom portion of the opening
Implementation Method 2
epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr
Implementation Method 3
epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas
Implementation Method 4
performing the method in an integrated cluster tool without an air break or intermediate wet preclean process, wherein the rate of the hydrogen chloride gas is approximately 70 sccm, performing the method in a process to form a backside power via for a transistor structure, and/or forming a self-aligned epitaxial source/drain structure of a transistor on the sacrificial fill material
Data Source
AI summary
A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 seem to approximately 90 seem in a chamber pressure of approximately 1 Torr to approximately 100 Torr.