Backside Power Rail FinFET via Extended Source Trench
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Solution Overview
Problem
Conventional integrated circuits face increased voltage drop and power consumption due to the scaling down of power rails, which existing semiconductor fabrication approaches have not adequately addressed.
Innovation Solution
The implementation of backside power rails and self-aligned vias in FinFET devices, which increases the number of metal tracks for connecting source/drain contacts and enhances gate density, while reducing power rail resistance by using wider dimensions and isolating backside power rails from nearby conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are scaled down to fit smaller integrated circuits, then device integration increases, but voltage drop and power consumption increase
Solution Approach 1:
The patent introduces backside power rails that extend from the backside of the substrate through vias to connect with frontside source/drain regions. This three-dimensional approach adds a vertical dimension to power distribution, allowing power rails to be positioned both on the frontside and backside of the device, thereby reducing resistance and power consumption while maintaining high integration density.
2Productivity
If power rail dimensions are reduced for scaling, then more devices can be integrated, but power rail resistance increases
Solution Approach 1:
By extending power rails to the backside of the substrate and connecting them via vertical vias, the patent creates additional current paths in the vertical dimension. This reduces the effective resistance of power distribution by providing multiple parallel conduction paths, thereby improving reliability without sacrificing integration density.
Solution Approach 2:
The backside power rails are positioned beneath the active device region, nesting the power distribution infrastructure within the overall device structure. This allows the power rails to occupy space that would otherwise be unused, providing low-resistance power delivery while maintaining high device integration.
3Ease of manufacture
If conventional fabrication approaches are used, then manufacturing simplicity is maintained, but voltage drop and power consumption problems persist
Solution Approach 1:
The patent segments the power distribution system into frontside power rails, backside power rails, and connecting vias. This segmentation allows each component to be optimized independently - frontside rails for local power delivery, backside rails for low-resistance power distribution, and vias for vertical interconnection - thereby reducing overall power consumption while using standard fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces power rail resistance and increases gate density, leading to improved performance and reduced power consumption in integrated circuits by providing additional connectivity and isolation in semiconductor structures.
Implementation Method 1
Etching an extended source trench in the FinFET device
Data Source
AI summary
A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.