Backside Power Rail Structure With Self-Aligned Vias for Gate Density
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Solution Overview
Problem
Conventional integrated circuits face increased voltage drop and power consumption due to scaled-down power rails, necessitating improved power rail designs in semiconductor fabrication.
Innovation Solution
Implementing backside power rails and self-aligned vias in semiconductor devices, particularly for gate-all-around transistors and FinFETs, to enhance metal track availability and reduce resistance, alongside methods for isolating these rails from nearby conductors and reducing resistance between power rails and source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are scaled down to match transistor dimensions, then device integration is improved, but voltage drop and power consumption increase
Solution Approach 1:
The patent introduces backside power rails that extend from the front surface through the substrate to the back surface, adding a vertical dimension to power delivery. This three-dimensional power rail structure provides additional current paths and reduces resistance without increasing planar footprint, thereby maintaining device integration while reducing power loss.
Solution Approach 2:
The power rail system is segmented into front surface power rails and backside power rails that are electrically connected through vertical vias. This segmentation creates multiple parallel current paths, reducing overall resistance and voltage drop while maintaining compact device dimensions.
2Productivity
If power rail width is reduced to increase transistor density, then gate density improves, but power rail resistance increases
Solution Approach 1:
By extending power rails to the backside of the substrate and utilizing vertical interconnects, the patent creates additional current pathways that compensate for the reduced width of individual power rails. This maintains low resistance while allowing narrower front-surface power rails that accommodate higher gate density.
Solution Approach 2:
The front surface power rails and backside power rails are merged through vertical vias to form a unified three-dimensional power network. This combined structure provides redundant current paths and reduces overall resistance while enabling narrower individual rail widths for increased gate density.
3Reliability
If backside power rails are added to reduce resistance, then power delivery improves, but device complexity increases
Solution Approach 1:
The backside of the substrate serves multiple functions: it acts as a mechanical support surface, a thermal management interface, and now as a carrier for power rails. This multi-functionality allows the backside structure to provide enhanced power delivery without proportionally increasing device complexity.
Solution Approach 2:
Vertical vias serve as intermediaries that electrically connect the front surface power rails to the backside power rails. These intermediary structures enable the three-dimensional power network while maintaining a systematic and manageable fabrication process through standard via formation techniques.
4Manufacturing precision
If self-aligned vias are used to connect power rails, then manufacturing precision improves, but process complexity increases
Solution Approach 1:
The via alignment structures are formed preliminarily during the transistor fabrication process, using the same lithography and etching steps that define the transistor geometry. This preliminary formation of alignment features ensures precise via placement without requiring separate alignment processes, thereby maintaining manufacturing precision while limiting process complexity increases.
Data Source
AI summary
A semiconductor structure includes a source/drain; one or more channel layers connected to the source/drain; a gate structure adjacent the source/drain and engaging each of the one or more channel layers; a first silicide layer over the source/drain; a source/drain contact over the first silicide layer; a power rail under the source/drain; one or more first dielectric layers between the source/drain and the power rail; and one or more second dielectric layers under the first silicide layer and on sidewalls of the source/drain, wherein the one or more second dielectric layers enclose an air gap.