Backside Power Rail Integration Without FEOL Contamination
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Solution Overview
Problem
Existing integrated circuit devices face challenges in forming power rails without contaminating transistor elements or undergoing high temperature processes that increase resistance.
Innovation Solution
The formation of a power rail is delayed until after the back-end-of-line (BEOL) portion of device fabrication, ensuring that metal elements do not contaminate transistors and avoiding high temperature processes associated with the front-end-of-line (FEOL) portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If power rail is formed during front-end-of-line (FEOL) portion, then power distribution network can be established early, but metal elements contaminate transistors and high temperature processes increase resistance
Solution Approach 1:
The fabrication process is divided into distinct segments: FEOL for transistor formation, BEOL for interconnect formation, and a separate subsequent process for power rail formation. This segmentation allows each component to be optimized independently, avoiding contamination while ensuring proper integration.
Solution Approach 2:
Transistors and interconnect structures are prepared in advance during FEOL and BEOL processes, with designated regions and contact structures ready to receive the power rail. The power rail is then formed later by etching through the substrate and depositing conductive material in the prepared regions.
2Productivity
If power rail is formed early in fabrication, then integration density can be increased, but contamination of transistor elements occurs
Solution Approach 1:
The power rail formation is extracted from the traditional FEOL/BEOL sequence and performed as a separate subsequent process. This extraction eliminates the contamination risk while maintaining the ability to achieve high integration density through precise positioning and substrate etching techniques.
Solution Approach 2:
The substrate itself serves as an intermediary medium, allowing the power rail to be formed by etching through it and depositing conductive material. This intermediary approach enables clean formation of the power rail without direct contact between metal deposition processes and transistor regions, preventing contamination while achieving integration.
3Ease of manufacture
If high temperature processes are used during FEOL, then transistor formation is completed, but resistance of power rail increases
Solution Approach 1:
Transistor fabrication is completed in advance during FEOL with all necessary contact structures and interconnect patterns prepared. The power rail is then added later in a low-temperature process, ensuring that no high-temperature exposure occurs after the power rail conductive material is deposited, thereby maintaining low resistance.
Solution Approach 2:
The process temperature parameter is changed from high temperature during FEOL to low temperature during power rail formation. This parameter change ensures that the conductive material deposited for the power rail is not subjected to thermal annealing that would increase resistance, while still allowing proper formation of the conductive structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents contamination and reduces resistance issues, resulting in a more reliable and efficient power delivery network within integrated circuit devices.
Implementation Method 1
forming a trench extending through the substrate by etching a second surface of the substrate
Data Source
AI summary
Methods of forming an integrated circuit devices may include forming a transistor on a first surface of a substrate. The transistor may include an active region, a source/drain region contacting the active region and a gate electrode on the active region. The methods may also include forming a conductive wire that is electrically connected to the source/drain region, forming a trench extending through the substrate by etching a second surface of the substrate, which is opposite the first surface of the substrate, and forming a power rail in the trench. The power rail is electrically connected to conductive wire.