Backside Power Rail Layout for Misalignment-Tolerant nTSV Landing
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Solution Overview
Problem
The challenge in semiconductor device fabrication is the misalignment of electrical contacts with buried power rails due to the large thickness of silicon substrates and the small size of nano through-silicon vias (nTSV) landing areas, leading to higher resistance and reliability issues.
Innovation Solution
The method involves forming a wider bottom portion of trenches to create a lateral footing area for improved nTSV to BPR landing, allowing for increased flexibility and minimizing misalignments by widening the landing area, thus ensuring reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nTSV is used to connect to BPR through thick substrate, then electrical connection is enabled, but misalignment occurs leading to higher resistance and reliability issues
Solution Approach 1:
The patent transitions from a single-point contact configuration to a distributed area contact configuration by forming multiple pad structures at the BPR landing zone. This dimensional expansion from point-to-area contact provides alignment tolerance, allowing the nTSV to connect reliably to the BPR even with manufacturing variations in the thick substrate environment.
Solution Approach 2:
The patent divides the single BPR contact into multiple segmented pad structures distributed across the BPR surface. This segmentation creates multiple potential contact points, so that even if one pad is misaligned, other pads can maintain electrical connection, thereby improving overall reliability and reducing the impact of single-point alignment errors.
2Strength
If substrate thickness is increased for mechanical strength, then device robustness is improved, but nTSV alignment with BPR becomes more difficult
Solution Approach 1:
The patent compensates for the alignment difficulty introduced by thick substrates by expanding the contact interface from a single point to multiple distributed pads in the lateral dimension. This provides alignment tolerance that offsets the increased difficulty of precise nTSV placement through the thick substrate.
Solution Approach 2:
The patent proactively addresses potential misalignment issues by pre-forming multiple pad structures that act as cushioning elements. These pads are positioned to accommodate expected alignment variations, so that even if the nTSV does not align perfectly with the center of any single pad, electrical connection is maintained through the distributed pad array.
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.