Backside Power Rail Layout for Dense IC Power Gating
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Solution Overview
Problem
Existing power gating designs in three-dimensional integrated circuits face challenges due to the vertical and lateral alignment of local and global power rails, which occupy significant silicon area and reduce transistor density.
Innovation Solution
The power rails and ground rails are spatially separated and positioned at different lateral levels in the backside structure, with connectors and dielectric layers to facilitate power distribution and reduce conductor crowding, allowing for more efficient use of silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If local VDD rails and global VDD rails are vertically stacked or laterally aligned, then power distribution is simplified, but silicon area is occupied and transistor density is reduced
Solution Approach 1:
The patent transitions from two-dimensional planar alignment of power rails to three-dimensional spatial separation. Local VDD rails and global VDD rails are positioned at different lateral levels rather than being stacked or aligned on the same plane, utilizing the third dimension (lateral positioning) to resolve the area occupation problem while maintaining simplified power distribution connectivity.
2Area of moving object
If power rails are spatially separated at different lateral levels, then transistor density increases, but interconnect complexity increases
Solution Approach 1:
The patent introduces middle of line connectors as intermediary elements that facilitate electrical connection between power gating transistors and upper interconnect layers. These connectors serve as mediation points that simplify the interconnect structure by providing dedicated connection paths, thereby reducing the overall interconnect complexity despite the spatial separation of power rails at different lateral levels.
3Loss of energy
If transistors are used to route power from global VDD rails to local VDD rails, then power gating is achieved, but leakage current increases
Solution Approach 1:
The patent applies local quality by using high-threshold voltage PMOS and NMOS transistors specifically at the power gating cell locations where power routing occurs. These high-VT transistors are strategically placed to disconnect global VDD rails from local VDD rails in inactive regions, providing localized leakage reduction without affecting the performance of active circuit blocks. The spatial separation of power rails further enhances this local quality control by isolating powered and unpowered regions.
Data Source
AI summary
An integrated circuit includes a frontside structure which includes a plurality of power gating transistors and at least one metalization layer above the power gating transistors. The circuit includes a backside structure below the power gating transistors of the frontside structure. The backside structure includes at least one global power rail, one local power rail and one ground rail. The global power rail, the local power rail and the ground rail are spatially separated from each other and are not laterally aligned.