Backside Power Rail Contacts With Recessed Source/Drain for Lower Cgd
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing capacitance between the gate electrode and source/drain regions during the formation of backside source/drain contacts, which degrades device performance due to increased complexity in metal layer routing and integration density.
Innovation Solution
A method is introduced where a portion of the source/drain feature is recessed to the level of an inner spacer during backside contact formation, using a sacrificial liner to protect the isolation region and align the backside contact, thereby reducing capacitance and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside source/drain contacts are formed with source/drain features at the original level, then contact formation is simpler, but capacitance between gate electrode and source/drain regions increases degrading device performance
Solution Approach 1:
The source/drain features are recessed to a lower level before backside contact formation, and a sacrificial liner is deposited in advance to protect the isolation region. This preliminary preparation enables subsequent alignment and contact formation while maintaining reduced capacitance and protecting surrounding structures.
Solution Approach 2:
A sacrificial liner is introduced as an intermediary protective layer between the isolation region and the etching process. This liner temporarily protects the isolation region during contact hole formation, allowing precise alignment without damaging surrounding structures, and is removed after serving its protective function.
2Reliability
If source/drain features are recessed to reduce capacitance, then device performance improves, but alignment precision requirements increase
Solution Approach 1:
Traditional mechanical alignment methods are replaced with self-aligned processes where the sacrificial liner and recessed features automatically define the contact position. The alignment is achieved through the physical structure itself rather than external alignment tools, improving precision and reducing variability.
Solution Approach 2:
The depth and dimensions of the recess are carefully controlled to optimize the balance between capacitance reduction and alignment ease. By adjusting the recess depth parameter, the patent achieves sufficient capacitance reduction while maintaining manufacturable alignment tolerances through the self-aligned sacrificial liner approach.
3Productivity
If minimum feature size is reduced to increase integration density, then more components fit on chip, but metal layer routing complexity increases
Solution Approach 1:
The patent moves power rail connections to the backside of the substrate, utilizing the third dimension (substrate thickness) to resolve routing congestion. By forming contacts and power rails on the backside, the patent creates additional routing space that separates power distribution from signal routing layers, reducing overall metal layer complexity while maintaining high integration density.
Data Source
AI summary
Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.