Backside Power Rail Architecture for Memory Area Efficiency
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Solution Overview
Problem
Conventional memory designs suffer from area inefficiency due to the use of frontside power rails for memory cells, leading to a need for improved area efficiency in modern memory architecture.
Innovation Solution
The implementation of a backside power rail architecture that provides power distribution networks for memory applications, utilizing both frontside and backside power rails to supply core and periphery voltages to memory control circuitry, with buried power rails and transition vias for efficient power coupling between domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If frontside power rails are used for memory cells, then voltage distribution to memory cells is achieved, but area efficiency deteriorates due to area penalty in fabrication
Solution Approach 1:
The patent applies dimensionality change by moving power distribution from the frontside (2D plane) to the backside of the substrate. Buried power rails are formed in the backside of the substrate, allowing power to be distributed through a third dimension (depth), thereby eliminating area penalties on the frontside while maintaining voltage distribution capability to memory cells and control circuitry
2Reliability
If conventional power rail architecture is used, then power distribution is achieved, but current-resistance drop increases reducing performance
Solution Approach 1:
The patent segments the power distribution system into multiple independent backside power rails that can be independently optimized. By dividing the power distribution function across multiple segmented rails with different voltage domains, the system reduces current density in each rail, thereby reducing I²R losses and improving overall performance
3Adaptability or versatility
If single power domain architecture is used, then fabrication is simplified, but adaptability deteriorates due to inability to support multiple voltage domains
Solution Approach 1:
The patent applies local quality by creating different voltage domains in different regions of the backside substrate. Each region can have tailored power rail characteristics (voltage level, current capacity) suited to its specific function, allowing simultaneous support for memory cell voltage, control logic voltage, and I/O voltage without requiring a single complex distribution network
Data Source
AI summary
Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.