Back-Side Power Rail Interconnects With 2D Monolayer Contacts
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Solution Overview
Problem
Integrated chips face challenges with high voltage drops, high resistance, low reliability, and increased RC delay due to small metal source/drain contact and wire dimensions, high resistivity of copper wires, and high capacitance, leading to electromigration and time-dependent dielectric breakdown issues.
Innovation Solution
The use of a stack of conductive monolayers, such as graphene or transition metal dichalcogenides, for the source/drain contact and wire, which allows for larger dimensions, lower resistivity, higher current density, and reduced capacitance, thereby reducing voltage drops, resistance, and RC delay while enhancing reliability and dielectric breakdown resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper wires are used for interconnects, then electrical conductivity is improved, but voltage drops and resistance increase due to high resistivity
Solution Approach 1:
The patent changes the material parameter from copper to graphene, which has fundamentally different electrical properties. Graphene's superior electrical conductivity and lower resistivity directly reduce voltage drops and resistance, resolving the contradiction between maintaining conductivity and reducing energy loss.
Solution Approach 2:
The patent employs a composite structure where graphene is integrated with existing semiconductor interconnect architectures. This composite approach combines the low resistivity of graphene with the structural benefits of traditional interconnect designs, achieving reduced voltage drops while maintaining reliability.
2Length of moving object
If metal source/drain contact dimensions are reduced, then device scaling is improved, but resistance increases and reliability decreases
Solution Approach 1:
The patent changes the material composition of source/drain contacts from traditional metals to graphene. This parameter change enables smaller contact dimensions while maintaining low resistance because graphene's intrinsic electrical properties compensate for the reduced cross-sectional area, thus improving scaling without sacrificing reliability.
Solution Approach 2:
The patent substitutes traditional metal-based electrical contacts with a graphene-based system. This substitution replaces the mechanical and electrical properties of metals with those of a two-dimensional material, enabling reduced dimensions while maintaining or improving electrical performance and reliability.
3Area of moving object
If wire dimensions are reduced, then integration density is improved, but RC delay increases due to higher resistance and capacitance
Solution Approach 1:
The patent changes the interconnect material from copper to graphene, fundamentally altering the resistance parameter. Graphene's lower resistivity compensates for reduced wire dimensions, while its atomic thickness reduces capacitance. This parameter change enables smaller wire areas without increasing RC delay, thus improving integration density while maintaining signal speed.
Solution Approach 2:
The patent transitions from three-dimensional bulk metal wires to a two-dimensional graphene structure. This dimensionality change reduces the effective capacitance by minimizing the wire's interaction with surrounding dielectric materials, while the high in-plane conductivity of graphene maintains low resistance even at reduced dimensions, thereby reducing RC delay.
4Ease of manufacture
If copper wire resistivity is high, then manufacturing is simplified, but electromigration and dielectric breakdown occur
Solution Approach 1:
The patent changes the material parameter from copper to graphene, which has fundamentally superior electrical and mechanical properties. Graphene's high electron mobility and strength prevent electromigration, while its stability reduces dielectric breakdown risks. This parameter change maintains manufacturing feasibility through established CVD techniques while dramatically improving reliability.
Solution Approach 2:
The patent substitutes copper-based interconnects with a graphene-based system. This substitution replaces the electromigration-prone metal with a two-dimensional material that exhibits superior resistance to electromigration and dielectric breakdown, thereby improving reliability while maintaining ease of manufacture through scalable deposition methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution results in lower voltage drops, reduced RC delay, improved reliability, and enhanced time-dependent dielectric breakdown resistance, addressing the limitations of traditional copper-based interconnects by utilizing two-dimensional materials with low resistivity and high current densities.
Implementation Method 1
The use of a stack of conductive monolayers, such as graphene or transition metal dichalcogenides, for the source/drain contact and wire, which allows for larger dimensions, lower resistivity, higher current density
Data Source
AI summary
The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a first source/drain structure, a second source/drain structure, a stack of channel structures, and a gate structure. The stack of channel structures and the gate structure are between the first and second source/drain structures. The gate structure surrounds the stack of channel structures. A first conductive wire overlies and is spaced from the semiconductor device. The first conductive wire includes a first stack of conductive layers. A first conductive contact extends through a dielectric layer from the first conductive wire to the first source/drain structure. The first conductive contact is on a back-side of the first source/drain structure.