Backside Power Rail Layout for Low-Resistance Nano-FET Integration
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Solution Overview
Problem
As semiconductor devices, such as nano-FETs, continue to shrink in feature size, challenges arise in integrating more components while maintaining performance, including increased electrical resistance and limitations in power rail width, which affect integration density and efficiency.
Innovation Solution
The formation of a power rail on the backside of nano-FETs with a dielectric layer insulating it from channel regions, allowing for a wider power rail width and increased interconnect density, and the use of a gate-last process to enhance gate and channel region isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but electrical resistance increases and power rail width is limited
Solution Approach 1:
The power rail is moved from the front side to the back side of the semiconductor device, utilizing the third dimension (depth/substrate thickness) to resolve the spatial conflict. This allows the power rail to be positioned beneath the channel regions, enabling wider power rail width without occupying front-side space, thereby reducing electrical resistance while maintaining high integration density
2Reliability
If power rail width is increased to reduce electrical resistance, then power delivery improves, but frontside space is constrained limiting further width increases
Solution Approach 1:
The power rail is repositioned to the back side of the substrate, utilizing the vertical dimension to escape the two-dimensional space constraint on the front side. This enables the power rail to achieve greater width by extending laterally beneath the channel regions without competing for front-side real estate, thus reducing electrical resistance
3Ease of manufacture
If power rail is placed on frontside with first metal layer interconnect, then interconnect structure is formed, but power rail width is constrained by interconnect spacing requirements
Solution Approach 1:
The power rail is positioned on the back side of the substrate, separated from the front-side interconnect structure by the substrate thickness. This spatial separation removes the constraint of interconnect spacing requirements on power rail width, allowing the power rail to be widened without affecting front-side interconnect formation
Solution Approach 2:
The device is divided into front-side and back-side functional regions. The front side contains the interconnect structure and active device regions, while the back side houses the widened power rail. This segmentation allows each region to be optimized independently without mutual constraint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electrical resistance and increases both first metal layer interconnect density and gate density by enabling a wider power rail width without the constraints of frontside power rail limitations, improving overall semiconductor device performance.
Implementation Method 1
a dielectric layer over the power rail... the dielectric layer insulates the power rail from the channel regions
Data Source
AI summary
Nanostructure field-effect transistors (nano-FETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a power rail, a dielectric layer over the power rail, a first channel region over the dielectric layer, a second channel region over the first channel region, a gate stack over the first channel region and the second channel region, where the gate stack is further disposed between the first channel region and the second channel region and a first source/drain region adjacent the gate stack and electrically connected to the power rail.