Back-Side Power Rail Layout for Low-Capacitance Nano-FETs
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components without increasing parasitic capacitance and improving transistor performance, particularly in avoiding unwanted contacts to source/drain regions that can reduce efficiency and increase capacitance.
Innovation Solution
A semiconductor device design is implemented with a device layer containing nanostructure field effect transistors (nano-FETs) where the back-side interconnect structure provides dedicated power rails, avoiding contacts to the front-sides of source/drain regions, which reduces parasitic capacitance and frees up space for additional interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnect structures with front-side contacts to source/drain regions are used, then electrical connectivity is achieved, but parasitic capacitance increases and transistor performance deteriorates
Solution Approach 1:
The patent moves the power rail contacts from the front side to the back side of the device layer, utilizing the third dimension (vertical stacking) to resolve the contradiction. By forming contacts to source/drain regions through the substrate from the back side, the design eliminates front-side parasitic capacitance while maintaining electrical connectivity, thus improving transistor performance without sacrificing connectivity.
Solution Approach 2:
The patent inverts the conventional contact approach by forming power rail contacts from the back side of the substrate rather than from the front side. This inversion allows contacts to be made to source/drain regions without creating parasitic capacitance on the front side, thereby improving transistor performance while maintaining connectivity.
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent segments the interconnect structure into front-side signal interconnects and back-side power rail interconnects. This segmentation allows independent optimization of each interconnect type and simplifies the manufacturing process by enabling separate formation steps, thereby reducing overall manufacturing complexity while maintaining high integration density.
Solution Approach 2:
By utilizing the back side of the substrate for power rail contacts, the patent effectively adds a second layer of interconnect routing in the vertical dimension. This dimensional change doubles the available routing space without increasing lateral complexity, enabling higher integration density while keeping manufacturing processes manageable.
3Productivity
If front-side contacts are formed to source/drain regions, then electrical connectivity is achieved, but space is consumed that could be used for additional interconnects
Solution Approach 1:
The patent resolves the space constraint by moving power rail contacts to the back side of the substrate, utilizing the vertical dimension for routing. This frees up the entire front side area for signal interconnects and active devices, effectively doubling the available lateral space for interconnect routing and significantly improving integration density.
Solution Approach 2:
By inverting the contact formation approach and making power rail contacts from the back side, the patent recovers front-side area that would otherwise be occupied by contact pads and via structures. This inversion frees up valuable lateral space for additional interconnect routing, enabling higher integration density.
Data Source
AI summary
In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.