Backside Power Rail Layout for Dense Nanosheet Source/Drain Contacts
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Solution Overview
Problem
The challenge of scaling down semiconductor devices to achieve increased device density and improved carrier mobility is hindered by the need for efficient processing and manufacturing techniques, particularly in the formation of nanosheet transistors.
Innovation Solution
A method for fabricating semiconductor devices with a stack of semiconductor layers and sacrificial layers, utilizing photolithography and etching processes to form fin structures, followed by the deposition and patterning of gate structures, dielectric materials, and epitaxial growth of source/drain features to create a semiconductor device structure with enhanced nanosheet channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is reduced to increase device density, then functional density increases, but manufacturing complexity and processing challenges increase
Solution Approach 1:
The device is segmented into distinct functional layers including alternating semiconductor layers (forming channels) and sacrificial layers. This segmentation allows for systematic fabrication through sequential deposition and patterning steps, making the complex nanosheet structure manufacturable despite its high density
Solution Approach 2:
Sacrificial layers are deposited and patterned in advance before the final semiconductor structures are formed. These preliminary sacrificial structures serve as templates that guide subsequent epitaxial growth and define the final device geometry, enabling precise control over the high-density nanosheet configuration
2Reliability
If nanosheet channels are used to achieve greater carrier mobility, then device performance improves, but contact resistance becomes more significant
Solution Approach 1:
Different regions of the device are given different properties: the nanosheet channels are engineered for high carrier mobility while the contact regions are specifically designed with optimized doping and geometry to minimize contact resistance. This local optimization allows each region to perform its specific function effectively
Solution Approach 2:
The contact structures are designed to nest around and make intimate contact with the nanosheet channels. The epitaxial source/drain features grow conformally on the nanosheets, ensuring maximum contact area and minimizing resistance while preserving the high-mobility channel properties
3Quantity of substance
If alternating semiconductor and sacrificial layers are deposited to form nanosheets, then device density increases, but manufacturing process complexity increases
Solution Approach 1:
The fabrication process utilizes changes in deposition parameters and epitaxial growth conditions to transition between forming sacrificial layers and forming active semiconductor channels. By systematically varying temperature, pressure, and precursor flows, the process achieves high-density structures through standardized manufacturing steps
Solution Approach 2:
The sacrificial layers act as intermediary structures that facilitate the formation of the final high-density nanosheet device. These intermediate layers are easily deposited and removed, serving as temporary templates that simplify the overall fabrication process while enabling the complex final structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-density nanosheet transistors with improved carrier mobility and reduced contact resistance, facilitating efficient manufacturing and performance enhancement.
Implementation Method 1
utilizing photolithography and etching processes to form fin structures
Implementation Method 2
utilizing photolithography and etching processes to form fin structures
Implementation Method 3
followed by the deposition and patterning of gate structures, dielectric materials
Implementation Method 4
epitaxial growth of source/drain features to create a semiconductor device structure
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first side and a second side opposing the first side, a source/drain epitaxial feature disposed adjacent the first side of the substrate, wherein the source/drain epitaxial feature comprises a first epitaxial layer, a second epitaxial layer in contact with the first epitaxial layer, and a third epitaxial layer having sidewalls surrounded by and in contact with the second epitaxial layer. The device structure also includes a first silicide layer in contact with the substrate, the first, second, and third epitaxial layers, a first source/drain contact extending through the substrate from the first side to the second side, and a first metal capping layer disposed between the first silicide layer and the first source/drain contact.