Backside Power Rail Packaging for Dense Hybrid-Bonded IC Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in increasing transistor density and reducing interconnect distances between integrated circuit (IC) dies while maintaining flexibility in die stacking and packaging, as feature sizes decrease, leading to complexities in power delivery and interconnect efficiency.
Innovation Solution
The implementation of hybrid bonding techniques for IC dies with backside power rails, which allows for the formation of stacked IC dies with backside power rails connected to source/drain regions through backside vias, enabling more efficient power delivery and increased flexibility in IC die stacking and packaging by reducing interconnect area and routing distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but power delivery and interconnect efficiency become more complex
Solution Approach 1:
The patent introduces backside power rails on the rear surface of IC dies, transitioning power delivery from a two-dimensional planar approach to a three-dimensional configuration. This allows power distribution to occur in the vertical dimension through backside vias connecting to source/drain regions, reducing interference with front-side signal routing and enabling higher integration density without proportionally increasing power delivery complexity
2Length of moving object
If interconnect distances between IC dies are reduced, then device density improves, but manufacturing flexibility and routing options are constrained
Solution Approach 1:
The patent segments the interconnect function into multiple independent pathways: front-side signal interconnects, backside power rails, and dedicated power vias. This segmentation allows each interconnect type to be optimized independently, enabling reduced interconnect distances for signaling while maintaining routing flexibility for power delivery through separate backside pathways
Solution Approach 2:
By moving power rails to the backside of dies and using vertical vias for power connection, the patent creates three-dimensional power distribution pathways that are independent of front-side signal routing. This dimensional separation maintains stacking flexibility while enabling shorter effective interconnect distances for both power and signal
3Use of energy by moving object
If backside power rails are implemented with hybrid bonding, then power delivery efficiency improves, but manufacturing process complexity increases
Solution Approach 1:
The patent combines hybrid bonding technology with backside power rail formation into an integrated manufacturing process. The hybrid bonding process simultaneously achieves die attachment and electrical interconnection, while backside vias are formed through the substrate to connect power rails to source/drain regions, consolidating multiple manufacturing steps into a unified process flow
Data Source
AI summary
Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.