Back-Side Power Rail Layout With Drain Recess for Lower IR Drop
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Solution Overview
Problem
Current semiconductor transistor devices face challenges with complex metal layer routing in the back-end-of-line (BEOL) process as they shrink beyond 3 nm, leading to increased mask requirements and voltage drop issues due to thin metal wires.
Innovation Solution
The solution involves relocating the power rail from the front side to the back side of the semiconductor transistor device, which relaxes metal layer routing, reduces the number of masks needed, and enhances the power rail and active region area, while using a recessed source/drain epitaxial structure and a back-side dielectric cap to minimize cell capacitance and eliminate current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the power rail is relocated from the front side to the back side of the semiconductor transistor device, then metal layer routing flexibility is improved and the number of masks needed is reduced, but the complexity of the device structure increases due to the need for recessed source/drain epitaxial structures and back-side dielectric caps
Solution Approach 1:
The power rail is moved from the front side (traditional planar dimension) to the back side of the device, utilizing the third dimension (depth/vertical stacking) to resolve routing conflicts. This dimensional transition allows metal layers to be routed more flexibly without increasing mask count, as the back-side placement provides additional spatial freedom for interconnect design.
Solution Approach 2:
The device structure is segmented into distinct functional regions: the front side contains the active transistor elements while the back side houses the power rail and associated structures. This segmentation isolates the power distribution function from the signal processing function, reducing interference and simplifying the overall design by allowing independent optimization of each region.
2Reliability
If a recessed source/drain epitaxial structure is used to minimize cell capacitance, then electrical performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The source/drain epitaxial structures are formed with recesses preliminary to the final device assembly, rather than attempting to create the recesses after complete fabrication. This preliminary formation allows the recessed structures to be integrated naturally into the epitaxial growth process, reducing the need for additional complex processing steps later in manufacturing.
3Loss of energy
If the power rail area is enhanced by relocating to the back side, then IR drop is improved, but the device fabrication complexity increases
Solution Approach 1:
The back-side power rail structure is merged with the source/drain contact regions, allowing the power distribution network to be formed simultaneously with the contact formation process. This merging eliminates the need for separate power rail fabrication steps, reducing overall fabrication complexity while still achieving enhanced power rail area and reduced IR drop.
Data Source
AI summary
A method for forming a semiconductor transistor device includes forming a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The channel structure is formed by forming a stack of semiconductor layers. The gate structure is formed wrapping around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are formed on opposite endings of the channel structure. The gate contact is formed on the gate structure. The back-side source/drain contact is formed under the first source/drain epitaxial structure. The second source/drain epitaxial structure is formed to have a concave bottom surface.