Backside Power Rail Layout for Lower Resistance in Scaled Chips
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Solution Overview
Problem
Conventional integrated circuits face increased voltage drop and power consumption due to the scaling down of power rails, which affects their performance and efficiency.
Innovation Solution
The implementation of backside power rails and self-aligned vias in semiconductor devices, allowing for wider metal tracks and reduced resistance, while also eliminating the need for frontside contacts to source/drain features, thereby reducing coupling capacitance and enhancing device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are scaled down to fit smaller integrated circuits, then device integration is improved, but voltage drop increases and power consumption increases
Solution Approach 1:
The patent introduces backside power rails as a third-dimensional solution, moving power delivery from the planar frontside to the vertical backside of the substrate. This dimensional transition allows power rails to be positioned below the transistor channel, eliminating the traditional top-side power delivery path and enabling wider, lower-resistance power tracks without occupying frontside device area.
Solution Approach 2:
The power delivery system is segmented into frontside and backside components. The frontside contains signal interconnects and transistor channels, while the backside carries dedicated power rails and contact structures. This segmentation allows independent optimization of power delivery paths from signal paths, enabling wider power tracks specifically for power delivery without compromising signal integrity or device density.
2Loss of energy
If power rail width is increased to reduce resistance, then power consumption is reduced, but device area increases
Solution Approach 1:
Power rails are relocated to the backside of the substrate, utilizing the vertical dimension to accommodate wider power tracks. This allows power rails to extend beyond the frontside device footprint, providing low-resistance power delivery paths without increasing the occupied device area on the frontside.
Solution Approach 2:
Instead of placing power rails above the transistors on the frontside, the patent inverts the approach by positioning power rails below the transistors on the backside. This inversion allows power delivery to occur from the opposite direction, enabling wider power tracks that do not conflict with frontside device structures.
3Object-generated harmful factors
If frontside contacts to source/drain features are eliminated, then coupling capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the contact function from the frontside to the backside of the substrate. Backside contact structures are formed that directly contact source and drain regions through the substrate thickness, eliminating the need for separate frontside contact formations and reducing the number of interconnect layers required on the frontside.
Solution Approach 2:
The contact formation process is merged with the backside processing sequence. Backside contacts are formed simultaneously with backside power rail structures using combined etch and fill processes, reducing the total number of discrete manufacturing steps compared to separate frontside and backside contact formations.
Data Source
AI summary
A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the first via.