Backside Power Rail Layout for Dense Logic Cell Scaling
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Solution Overview
Problem
In advanced semiconductor technologies with aggressive cell scaling, there is often not enough room to place buried power rails in the shallow trench isolation region, necessitating improved designs for backside power rail formation.
Innovation Solution
A semiconductor structure is developed with a backside power rail embedded within shallow trench isolation regions, connected via a via-to-backside power rail to metal contacts, and surrounded by a dielectric isolation liner, allowing power delivery through a backside interlayer dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional buried power rails are placed in the shallow trench isolation region, then power delivery is achieved, but device area is insufficient for advanced scaling
Solution Approach 1:
The patent moves the power rail from the traditional lateral position in the shallow trench isolation region to a vertical backside position, utilizing the third dimension (depth) to resolve the area constraint. The backside power rail is formed by etching through the substrate and filling with conductive material, allowing power delivery without occupying lateral device area.
2Productivity
If cell scaling is made more aggressive, then device density increases, but space for power rails decreases
Solution Approach 1:
By relocating power rails to the backside of the substrate, the invention frees up lateral space in the shallow trench isolation region for additional logic elements, thereby increasing device density while maintaining adequate power delivery infrastructure.
Solution Approach 2:
The power rail function is extracted from the shallow trench isolation region and placed in the backside interlayer dielectric, separating the power delivery function from the logic density-critical regions and enabling independent optimization of both.
3Reliability
If power rail thickness is increased, then voltage drops are reduced, but available space is consumed
Solution Approach 1:
The backside power rail structure allows for thicker conductive fills in the vertical dimension without consuming lateral space. The via-to-backside power rail provides a vertical connection path that enables robust power delivery with adequate current carrying capacity while preserving all lateral space for logic connections.
Data Source
AI summary
A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level located on a first side of the front-end-of-line level. A plurality of shallow trench isolation regions are located between adjacent field effect transistors, each of the plurality of shallow trench isolation regions being surrounded by a dielectric isolation liner. A backside power rail is located within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. A via-to-backside power rail embedded, at least in part, within a shallow trench isolation region is located between two field effect transistors of a similar polarity, the via-to-backside power rail is adjacent and electrically connected to at least one metal contact and extends from the at least one metal contact to a first surface of the backside power rail.