Backside Power Rail Routing for Semiconductor Scaling
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Solution Overview
Problem
As semiconductor devices scale down, routing both signal wires and power wires at the frontside of the substrate becomes increasingly challenging due to reduced space, leading to increased resistance and reduced power efficiency in power rail design.
Innovation Solution
The implementation of a frontside power via that enables backside power delivery, allowing for improved frontside signal routing flexibility by electrically connecting source/drain contacts to a backside metal layer, thereby reducing resistance and enhancing power efficiency through the use of power vias positioned at cell boundaries and stacked backside interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power wires are routed at the frontside of the substrate, then signal routing is simplified, but resistance increases and power efficiency decreases due to reduced space
Solution Approach 1:
The patent moves power wire routing from the traditional frontside (2D plane) to the backside of the substrate, utilizing the third dimension (depth/thickness) of the device structure. This dimensional transition allows power wires to be routed independently from signal wires, increasing power wire width and reducing resistance without compromising frontside signal routing complexity
2Loss of energy
If power wire width is increased to reduce resistance, then power efficiency improves, but frontside signal routing space is reduced
Solution Approach 1:
The patent segments the routing function by separating power wire routing from signal wire routing into different spatial locations. Power wires are routed on the backside while signal wires remain on the frontside, allowing each type of wire to be optimized independently for its specific function without competing for the same routing space
3Productivity
If device geometry is scaled down to increase functional density, then production efficiency improves, but routing space for power wires decreases
Solution Approach 1:
By transitioning power routing to the backside of the substrate, the patent effectively adds vertical dimensionality to the routing architecture. This allows continued scaling of frontside geometry for increased functional density while maintaining adequate power routing space on the backside, thus supporting both scaling and power delivery requirements
Data Source
AI summary
A device includes a stack of semiconductor nanostructures, a gate structure wrapping around the semiconductor nanostructures, a source/drain region abutting the gate structure and the stack, a contact structure on the source/drain region, a backside dielectric layer under the stack, and a via structure extending from the contact structure to a top surface of the backside dielectric layer.