Backside Power Rail Tapering to Prevent N2P Shorts
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Solution Overview
Problem
As transistor devices are scaled further, N2P (n-type FET to p-type FET) shorts in the backside power rail become a concern due to tight spacing, which can lead to electrical shorts and performance issues.
Innovation Solution
The formation of backside power rails with tapered vertical side surfaces and opposite tapering angles for neighboring rails, combined with a high-k dielectric spacer, is implemented to reduce shorts. This involves a subtractive metal etch for one rail and a damascene process for the other, ensuring opposite tapering directions and dielectric isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor devices are scaled further to reduce FET device footprint, then device density and integration are improved, but N2P shorts in backside power rail occur due to tight spacing
Solution Approach 1:
The patent applies asymmetry by forming adjacent backside power rails with opposite tapering directions. One rail has side walls tapering inward from top to bottom, while the adjacent rail has side walls tapering outward from top to bottom. This asymmetric configuration increases the spacing between rails at their closest point, preventing N2P shorts while maintaining compact overall device footprint for continued scaling.
Solution Approach 2:
The patent transitions from considering only horizontal spacing between power rails to utilizing the vertical dimension through tapered side walls. By controlling the tapering directions in the vertical dimension, the patent creates additional clearance between adjacent rails without increasing horizontal spacing, thus maintaining device density while preventing shorts.
2Productivity
If tight n-type FET to p-type FET spacing is implemented, then device integration density is improved, but electrical shorts between power rails occur
Solution Approach 1:
The patent uses asymmetric tapering of adjacent power rails where one rail tapers inward and the adjacent rail tapers outward. This creates a non-uniform spacing profile that maintains tight overall integration while ensuring sufficient clearance at critical points to prevent electrical shorts between n-type and p-type FET power rails.
Solution Approach 2:
The patent introduces a dielectric spacer as an intermediary element between adjacent backside power rails. This spacer physically separates the rails and maintains electrical isolation, enabling tight spacing for high integration density while preventing harmful electrical interactions between n-type and p-type FET power supplies.
3Ease of manufacture
If conventional parallel tapering of backside power rails is used, then manufacturing simplicity is maintained, but electrical shorts occur due to insufficient spacing
Solution Approach 1:
The patent modifies the conventional symmetric tapering approach by implementing opposite tapering directions for adjacent power rails. This asymmetric configuration can be achieved through selective etching processes and provides sufficient spacing to prevent shorts while remaining compatible with standard semiconductor manufacturing techniques.
Solution Approach 2:
Instead of having adjacent power rails taper in the same direction (conventional approach), the patent inverts the approach by having adjacent rails taper in opposite directions. One rail tapers inward while the adjacent rail tapers outward, creating natural spacing that prevents electrical shorts.
Data Source
AI summary
A first power rail directly below and connected to a source-drain epitaxy region of a positive field effect transistor (p-FET) region, a second power rail directly below and connected to a source-drain epitaxy region of a negative field effect transistor (n-FET) region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other. Forming a first power rail by subtractive metal etch, where the first power rail is directly below and connected to a source-drain epitaxy region of a p-FET region and forming a second power rail by damascene process, where the second power rail is directly below and connected to a source-drain epitaxy region of an n-FET region, the first power rail and the second power rail each comprise vertical side surfaces which taper in an opposite direction from each other.