Backside Power Rail Trench Layout for Low-Capacitance Semiconductors
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling integration density while maintaining electrical stability and reducing capacitance between contacts, particularly with the use of multi-gate transistors.
Innovation Solution
The semiconductor device incorporates a substrate with active patterns, a field insulating film, a power rail, and a metal pattern, featuring a trench with a convex sidewall and a metal pattern that connects to the power rail, along with a power rail via, to enhance electrical connectivity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch size is decreased to increase integration density, then integration density is improved, but capacitance between contacts increases and electrical stability deteriorates
Solution Approach 1:
The invention transitions from a planar contact structure to a three-dimensional structure by forming a trench in the substrate and filling it with a metal pattern. This vertical dimensionality change allows contacts to be positioned at different depths, reducing lateral proximity and capacitance between contacts while maintaining high integration density.
Solution Approach 2:
The invention introduces a dielectric layer as an intermediary between the metal pattern and the active region, and between adjacent metal patterns. This dielectric mediator reduces parasitic capacitance and provides electrical isolation, thereby improving electrical stability while enabling closer spacing for higher integration density.
2Productivity
If multi-gate transistors are used to increase integration density, then integration density is improved, but contact capacitance increases
Solution Approach 1:
By forming contacts vertically within trenches rather than laterally on the surface, the invention reduces the overlapping area between contacts and active regions. This dimensional reconfiguration decreases parasitic capacitance while supporting the high-density multi-gate transistor architecture.
Solution Approach 2:
The invention extracts the contact structure from the planar surface and relocates it into subsurface trenches. This separation removes the harmful capacitive coupling that would otherwise exist between closely spaced surface contacts and active regions, enabling higher integration density with reduced capacitance.
Data Source
AI summary
A semiconductor device includes: a substrate including an upper surface and a lower surface opposite to the upper surface; an active pattern disposed on the upper surface of the substrate and extending in a first direction; a field insulating film disposed on the upper surface of the substrate and covering a sidewall of the active pattern; a power rail disposed on the lower surface of the substrate and extending in the first direction; a trench formed in the substrate and exposing a portion of the power rail; and a metal pattern filling at least a portion of the trench and connected to the power rail, wherein a bottom surface of the trench is substantially coplanar with the lower surface of the substrate, wherein a sidewall of the trench has a convex shape, and wherein at least a portion of the field insulating film is disposed in the trench.