Backside Power Rail Vias for Dense Cells and Better Electrostatics
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Solution Overview
Problem
The need for semiconductor devices with reduced cell area usage for connecting to power rails and improved transistor structure to enhance electrostatic coupling and reduce parasitic capacitance and off-state leakage.
Innovation Solution
A method of forming semiconductor devices by creating via openings from the top surface to the bottom surface of the wafer device, depositing metal in these openings, bonding the bottom surface to a bonding wafer, and optionally thinning the substrate to form contacts, allowing for backside power rail connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rail connections are made on the front of the cell, then electrical connectivity is achieved, but cell area is significantly consumed
Solution Approach 1:
The patent inverts the conventional approach by moving power rail connections from the front of the cell to the backside of the substrate. This is achieved by forming via openings through the substrate to reach the bottom surface of the wafer device, depositing metal in these vias, and bonding the bottom surface to a bonding wafer. This inversion allows power rail connections to be established without consuming significant cell area on the front surface.
Solution Approach 2:
The patent transitions the power rail connection approach from a two-dimensional surface connection to a three-dimensional through-substrate connection. By forming deep vias that extend through the substrate thickness and making connections on the backside surface, the solution utilizes the third dimension (substrate depth) to achieve connectivity without occupying additional planar cell area.
2Productivity
If transistor feature sizes are shrunk to achieve greater circuit density, then integration increases, but electrostatic coupling deteriorates and parasitic capacitance increases
Solution Approach 1:
The patent addresses electrostatic coupling challenges by transitioning to a three-dimensional device architecture with vertical channel regions. The via openings extend deeply through the substrate to reach the bottom surface of the wafer device, enabling power rail connections that are closer to the active transistor regions. This vertical approach improves electrostatic control by reducing the distance between power rails and transistor channels, thereby enhancing coupling efficiency despite reduced feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cell area required for power rail connections and improves transistor performance by enhancing electrostatic coupling and reducing parasitic capacitance.
Implementation Method 1
depositing a metal in the via opening
Implementation Method 2
depositing a metal in the via opening
Implementation Method 3
bonding the bottom surface of the wafer device to a bonding wafer
Data Source
AI summary
Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.