Backside Power Rails and Air Gaps in Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor fabrication methods fail to effectively reduce resistance and coupling capacitance in power rails and vias on the backside of integrated circuits, leading to increased voltage drop and power consumption as circuits scale down.
Innovation Solution
The introduction of backside metal wiring layers and air gaps interposed between gate stacks and power rails, which reduces coupling capacitance and eliminates leakage paths, utilizing a bottom self-aligned capping layer with high dielectric constant materials for etching selectivity and air gaps to enhance isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form power rails above transistors, then connectivity is provided, but voltage drop increases and power consumption increases due to increased resistance
Solution Approach 1:
The patent introduces backside power rails formed on the opposite side of the substrate from the transistor gates, transitioning the power delivery system from a two-dimensional planar arrangement to a three-dimensional configuration that utilizes both sides of the substrate. This dimensional change allows power rails to be positioned closer to transistor sources and drains, reducing current path length and resistance, thereby decreasing voltage drop and power consumption.
Solution Approach 2:
The patent employs intermediate structures including via holes, dielectric layers, and self-aligned capping layers that facilitate electrical connection between backside power rails and frontside transistor contacts. These intermediary elements enable the backside rail architecture to function effectively by providing controlled access points and electrical pathways through the substrate thickness.
2Productivity
If power rails are scaled down with the circuit, then integration density increases, but resistance increases and voltage drop increases
Solution Approach 1:
By moving power rails to the backside of the substrate and utilizing the third dimension (substrate thickness), the patent enables power delivery without constraining lateral space. This allows continued scaling of frontside circuit elements for higher integration density while maintaining robust power rail dimensions on the backside that prevent resistance increase and voltage drop.
3Ease of operation
If conventional interconnect structures are used, then connectivity is achieved, but coupling capacitance increases and leakage paths exist
Solution Approach 1:
The patent introduces self-aligned capping layers and dielectric materials as intermediary structures between power rails and adjacent transistor components. These intermediaries provide electrical isolation that eliminates unwanted leakage paths and reduces coupling capacitance between power rails and signal lines, while still enabling necessary connectivity through controlled via holes.
4Ease of manufacture
If backside power rails are formed without air gaps, then manufacturing is simpler, but coupling capacitance increases and isolation is reduced
Solution Approach 1:
The patent introduces air gaps selectively in specific regions between power rails and transistor components, applying local quality changes rather than uniform structure throughout. The air gaps are formed only where isolation is needed, while other regions maintain direct contact structures for connectivity, thus reducing coupling capacitance locally without compromising overall manufacturability.
Solution Approach 2:
The patent utilizes the dielectric constant parameter by introducing air gaps (εr≈1) between power rails and adjacent structures, significantly reducing coupling capacitance compared to conventional dielectric materials (εr>3). This parameter change is achieved through selective removal of dielectric material or direct formation of air spaces during the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power rail resistance, increases gate density, and improves time-dependent dielectric breakdown performance, enabling faster operation and greater device integration without increasing circuit complexity.
Implementation Method 1
utilizing a bottom self-aligned capping layer with high dielectric constant materials for etching selectivity
Implementation Method 2
air gaps interposed between gate stacks and power rails, which reduces coupling capacitance
Data Source
AI summary
A method includes providing a structure having a substrate, a first dielectric layer over the substrate, one or more semiconductor channel layers over the first dielectric layer and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the one or more semiconductor channel layers; etching the substrate from the backside of the structure to form a first trench exposing the first S/D feature and a second trench exposing the second S/D feature; forming an S/D contact in the first trench; etching at least a portion of the first dielectric layer resulting in a portion of the S/D contact protruding from the first dielectric layer at the backside of the structure; and depositing a seal layer over the S/D contact, wherein the seal layer caps an air gap between the gate structure and the seal layer.