Self-Aligned Backside Power Rails for Flexible Cell Height Layouts
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Solution Overview
Problem
Existing backside power rail (BPR) technology faces challenges such as routing resistance, alignment margins, layout flexibility, and packing density in modern integrated circuits, limiting further scaling and performance enhancement.
Innovation Solution
The implementation of self-aligned backside interconnect structures with a grid-shaped arrangement of backside power rail interconnects, electrically separated by shallow trench isolation and diffusion break isolation regions, allowing for flexible cell height integration and hybrid or mixed cell heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional front-side power rails are used, then power delivery is provided, but routing resources are limited and layout flexibility is constrained
Solution Approach 1:
The patent moves power rails from the traditional front-side (planar dimension) to the backside of the substrate, utilizing the third dimension (vertical stacking) to provide power delivery. This dimensional transition frees up front-side routing resources and eliminates constraints on layout flexibility, as power rails no longer occupy precious front-side interconnect layers.
Solution Approach 2:
The power delivery network is segmented into front-side signal routing and backside power routing. By separating these functions spatially (front vs. back of substrate), the patent enables independent optimization of each function without mutual interference, thereby improving both routing resources and layout flexibility.
2Productivity
If backside power rails are implemented, then routing resources are freed up, but alignment precision and packing density face new challenges
Solution Approach 1:
The patent incorporates alignment marks and reference structures during the front-side fabrication process that extend to or are visible from the backside. These pre-formed references enable precise alignment of backside power rails without requiring additional complex alignment procedures, thereby maintaining manufacturing precision while freeing routing resources.
Solution Approach 2:
The backside power rail structure is designed to be self-aligning with front-side features through the use of through-substrate vias and self-aligned etching processes. The fabrication process itself provides the alignment references, eliminating the need for separate high-precision alignment steps and improving both productivity and manufacturing precision.
3Reliability
If power rail thickness is increased to reduce resistance, then power delivery efficiency improves, but substrate area occupied by power rails increases
Solution Approach 1:
By moving power rails to the backside of the substrate, the patent enables thicker power rail implementation without consuming additional front-side active area. The increased thickness reduces resistive losses and improves power delivery efficiency, while the backside location ensures that the area occupied does not interfere with front-side device placement and routing.
Data Source
AI summary
A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.