Backside Power Rail Interconnects for Dense Hybrid-Bonded IC Stacks
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing transistor density and reducing interconnect distances between integrated circuit (IC) dies while maintaining flexibility in die stacking and packaging, as smaller feature sizes lead to new problems that existing technologies have not effectively addressed.
Innovation Solution
The implementation of hybrid bonding techniques for IC dies, including the use of backside power rails and interconnect structures, allows for the formation of packaged semiconductor devices with increased transistor density, reduced interconnect distances, and enhanced flexibility in IC die stacking and packaging by connecting front-side and backside interconnects directly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional front-side interconnect routing is used, then device functionality is achieved, but interconnect distances are long and routing area is large
Solution Approach 1:
The patent introduces backside power rails that extend along the longitudinal edge of the semiconductor device, utilizing the third dimension (depth/edge routing) instead of only planar routing. This allows power delivery along the perimeter rather than through the chip area, reducing the distance power must travel through interconnect layers and enabling higher transistor density in the active area.
2Speed
If more interconnect layers are added to reduce routing distance, then signal transmission improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the power delivery function into two parts: front-side interconnects for local power distribution and backside power rails for long-distance power delivery along the edge. This segmentation allows each part to be optimized independently, reducing the need for additional complex interconnect layers while maintaining fast signal transmission.
3Quantity of substance
If chip area is increased to accommodate more components, then device functionality improves, but interconnect routing area increases
Solution Approach 1:
By routing power rails along the longitudinal edge of the device rather than through the chip area, the patent effectively removes power routing from the planar dimension. This allows components to be packed more densely in the active area without proportionally increasing the interconnect routing area, as power delivery occurs in a separate dimensional path along the perimeter.
Data Source
AI summary
Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.