Back-Side Partial-Substrate Power Rails for Low-Loss Routing
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges with introducing power and signal routing on the wafer back-side, including localized stress effects, interference with back-side circuit elements, and processing difficulties with through-silicon via interconnects, leading to resistance, capacitance, and power consumption issues.
Innovation Solution
The integration of conductive back-side ground and power-distribution conductive partial-substrate rail (PSR) structures with back-side decoupling capacitors, formed using selective implantation and femtosecond laser annealing, to create effective power and ground distribution while providing EMI shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If through-silicon via (TSV) interconnects are used for back-side power routing, then power delivery capability is improved, but localized stress effects and processing difficulty increase
Solution Approach 1:
The patent divides the back-side power routing into two separate conductor types: partial-substrate rail conductors (extending only partway through the substrate) and through-substrate via conductors (extending completely through). This segmentation allows each conductor type to be optimized for its specific function, reducing overall processing difficulty while maintaining power delivery capability.
Solution Approach 2:
The patent transitions from traditional planar front-side power routing to three-dimensional back-side routing with multiple conductor levels and types. By utilizing the substrate thickness dimension and creating conductors at different depths (partial vs. through), the patent achieves improved power delivery without proportionally increasing processing complexity.
2Loss of energy
If back-side power routing is introduced to reduce resistance and capacitance, then power consumption is improved, but interference with back-side circuit elements increases
Solution Approach 1:
The patent applies different conductor configurations in different regions of the back-side substrate. Partial-substrate rail conductors are used in regions where low resistance is critical, while through-substrate via conductors are used in regions requiring minimal interference with back-side circuit elements. This local differentiation allows simultaneous optimization of power consumption and reduction of harmful interference.
Solution Approach 2:
The patent introduces dielectric layers as intermediary structures between the back-side power conductors and back-side circuit elements (such as decoupling capacitors). These dielectric intermediaries electrically isolate the power routing from sensitive circuit elements, reducing interference while maintaining the low resistance path for power delivery.
3Ease of manufacture
If partial-substrate rail conductors are used instead of through-silicon vias, then processing compatibility is improved, but connectivity is reduced
Solution Approach 1:
The patent merges partial-substrate rail conductors and through-substrate via conductors into a unified back-side power distribution network. The partial rails provide broad coverage and ease of manufacturing, while the through-vias provide direct connectivity where needed. By combining these two conductor types, the patent achieves both processing compatibility and reliable connectivity.
Solution Approach 2:
The patent forms partial-substrate rail conductors before completing the substrate thinning process. This preliminary action allows the rail conductors to be created when the substrate is still thick enough to provide mechanical support, simplifying processing. Subsequent substrate thinning and through-via formation then build upon this preliminary structure, achieving both ease of manufacture and connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces resistance, capacitance, and power consumption, enhances connectivity, and provides EMI shielding, allowing for three-dimensional multi-die packaging without the need for keep-out-zones and stress concerns associated with through-silicon vias.
Implementation Method 1
annealing the implant regions at the bottom of back-side PSR trench openings with a femtosecond laser-anneal process
Implementation Method 2
femtosecond laser-anneal process
Implementation Method 3
providing a highly effective Electromagnetic Interference (EMI) shield
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A back-side ground and power-distribution network is formed on a semiconductor wafer substrate by selectively etching first and second back-side partial-substrate rail (PSR) trench openings through a back-side surface of the wafer substrate, selectively forming a plurality of defined n-type conductive regions and defined p-type conductive regions in the wafer substrate at the bottoms of the first and second back-side PSR trench openings in position for electrical contact with n-well and p-well regions, and then forming first and second back-side PSR conductors in the first and second back-side PSR trench openings to be directly electrically connected over the plurality of defined n-type conductive regions and defined p-type conductive regions to the n-well and p-well regions in the wafer substrate.