Backside Power Distribution Layout for IR Drop and Signal Isolation
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Solution Overview
Problem
Existing semiconductor devices face issues with significant voltage drop (IR drop) and power integrity due to the long power transmission path through top metal layers, which also limits the size reduction of semiconductor packages and causes interference with signal lines.
Innovation Solution
Implementing a backside power distribution network at the interface between a first substrate and a second substrate in semiconductor devices, which reduces the power transmission path length and minimizes IR drop, allowing for smaller semiconductor package sizes without interference issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power distribution network is located on top metal layers, then power can be transmitted to front end of line active devices, but significant voltage drop (IR drop) occurs and power integrity deteriorates
Solution Approach 1:
The power distribution network is inverted from the conventional top metal layer location to the substrate level, specifically implemented on the backside of the substrate. This inversion dramatically shortens the current path length, reducing the resistance and thus the IR drop, while still maintaining effective power delivery to the active devices.
Solution Approach 2:
The power distribution network transitions from a planar arrangement in the top metal layers to a three-dimensional configuration utilizing the substrate depth. By placing power delivery structures at the substrate level and using vertical interconnects, the patent creates a multi-layer power distribution architecture that reduces horizontal current path length.
2Power
If power rails and power lines are placed alongside signal lines in top metal layers, then power can be delivered to active devices, but semiconductor device size reduction is limited
Solution Approach 1:
By inverting the power distribution network to the substrate level, the patent separates power delivery from the top metal layer signal routing. This allows the active devices to be positioned more freely without being constrained by the need for adjacent power rails in the same metal layer, enabling greater device miniaturization.
3Power
If power lines are placed alongside signal lines in top metal layers, then power can be transmitted to active devices, but interference occurs within signal lines
Solution Approach 1:
The patent segments the power distribution function from the signal routing function by placing them in different spatial locations. Power distribution is implemented at the substrate level while signal lines remain in the top metal layers, physically separating the two functions and eliminating the interference problem that occurs when they are placed alongside each other.
Solution Approach 2:
The patent uses vertical dimensionality to separate power and signal paths. Power delivery structures are positioned at the substrate level (lower dimension) while signal lines occupy the top metal layers (upper dimension), creating a three-dimensional separation that eliminates electromagnetic interference while maintaining both functions.
Data Source
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AI summary
Novel tools and techniques are provided for implementing a semiconductor package or a chip package, and more particularly methods, systems, and apparatuses are provided for implementing a semiconductor package or a chip package including a backside power distribution network. In various embodiments, an apparatus includes a first substrate comprising a device configured to receive a voltage and a first side located on a front side of the first substrate and a second side located on a back side of the first substrate, a second substrate, the second substrate configured to support the first substrate, and a power distribution network located at an interface between the second side of the first substrate and the second substrate.