Backside Power Delivery Layout for Self-Aligned Source/Drain Contacts
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Solution Overview
Problem
Integrated circuit devices with power delivery networks on the backside face challenges in manufacturing complexity and reliability, requiring improved manufacturing processes and enhanced operational reliability.
Innovation Solution
A method involving the formation of a first etch stop layer on a substrate, followed by the creation of self-aligned source/drain regions and place holders, substrate removal to expose these features, and the formation of a base dielectric layer with a rear conductive line connected to the source/drain region, facilitating the integration of a power delivery network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a power delivery network is formed on the backside of integrated circuit devices, then power delivery efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The method performs preliminary actions by forming the etch stop layer and place holders on the front side of the substrate before substrate removal. This preliminary structuring enables subsequent backside processing to proceed with improved alignment and reduced complexity, as the place holders serve as pre-positioned reference points for rear conductive line formation
Solution Approach 2:
The invention inverts the conventional manufacturing sequence by removing the substrate to expose the formed structures, then continuing processing on the backside. This inversion allows the power delivery network to be formed on the backside rather than the front, improving power delivery efficiency while the pre-formed etch stop layer and place holders mitigate the expected increase in manufacturing complexity
2Manufacturing precision
If self-aligned source/drain regions are formed using place holders, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The place holders serve as intermediary structures that facilitate precise self-alignment of the source/drain regions. These temporary structures are formed first, then used as alignment references during subsequent etching and material deposition steps, enabling high manufacturing precision without requiring complex alignment systems
Solution Approach 2:
The method employs self-aligned fabrication where the place holders and etch stop layer automatically define the positions of source/drain regions through the etching process. The structures serve themselves as alignment references, eliminating the need for separate alignment operations and reducing overall process complexity despite the additional initial structuring steps
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A method of manufacturing an integrated circuit device may include forming a first etch stop layer (12) on a first face (10a) of a substrate (10); forming a gate structure (GL1) including a gate electrode layer (44a) and first and second source/drain regions (34A, 34B) on the first etch stop layer (12), the first and second source/drain regions (34A, 34B) respectively being self-aligned with opposing side walls of the gate structure (GL1) and lower portions of the first and second source/drain regions (34A, 34B) respectively contacting first and second place holders (32a, 32b) extending into the substrate (10); removing the substrate (10) until the first etch stop layer (12) is exposed from a second face of the substrate (10) while the first and second place holders (32a, 32b) are exposed; forming a base dielectric layer (74) on a rear side of the first and second place holders (32a, 32b); and forming a rear conductive line (86, 84, 82) electrically connected to the second source/drain region (34B).