Backside Power Routing in Semiconductor Source/Drain Structures
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Solution Overview
Problem
Current semiconductor devices face challenges in improving routing congestion and scaling size due to limitations in power delivery networks, particularly in three-dimensional structures.
Innovation Solution
A semiconductor device with a backside power delivery network is implemented using a streamlined manufacturing process, featuring a base insulation layer, channel layer, source/drain patterns, gate structure, lower wire structure, and through electrode, which connects the source/drain patterns to the lower wire structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If power delivery network is placed on the backside of the substrate, then routing congestion is improved and scaling capability is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The power delivery network is moved from the traditional planar configuration on the front side to the backside of the substrate, utilizing the third dimension (depth/thickness) to resolve routing congestion. This dimensional transition allows power and ground signals to be routed separately from signal paths, eliminating interference and improving scalability without increasing lateral manufacturing complexity.
Solution Approach 2:
The substrate is functionally segmented into front side (signal processing) and back side (power delivery), allowing independent optimization of each layer. This segmentation enables the power delivery network to be designed and manufactured separately, reducing overall system complexity while improving routing efficiency.
2Reliability
If through electrodes are used to connect source/drain patterns to lower wire structure, then electrical connectivity is improved, but manufacturing steps increase
Solution Approach 1:
Through electrodes are formed in the base insulation layer before final interlayer insulation deposition, establishing electrical connectivity pathways in advance. This preliminary action ensures reliable connections between source/drain patterns and lower wire structures are in place before subsequent manufacturing steps, reducing the need for additional alignment and connection steps.
Data Source
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AI summary
A semiconductor device may include a base insulation layer (100), a channel layer (CH) on a first surface of the base insulation layer (100), a first source/drain pattern (151) and a second source/drain pattern (152) spaced apart from each other in a first direction (D1) on a first surface of the base insulating layer (100) with the channel layer (CH) therebetween, a gate structure (GS) on the first surface of the base insulation layer (100) and extending in a second direction (D2) crossing the first direction (D1), a lower wire structure (220) on a second surface of the base insulation layer (100), and a through electrode (190) spaced apart from the gate structure with the first source/drain pattern (151) between the through electrode (190) and the gate structure. The through electrode (190) may penetrate the base insulation layer (100) and electrically connect the first source/drain pattern (151) to the lower wire structure (220). The first direction (D1) may be parallel to the first surface of the base insulation layer (100).