Backside Power Interconnect Routing for Faster SRAM Writes
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Solution Overview
Problem
Static random access memory (SRAM) devices face challenges in achieving efficient write operations due to limitations in power supply voltage levels, which affect the transition time between logic states, and existing solutions often introduce complexity and overhead.
Innovation Solution
The implementation of a power supply interconnect routing that routes above and below the substrate of memory cells, increasing interconnect resistance and resulting in a lower power supply voltage level at memory cells, thereby improving write operation performance without the need for additional write-assist circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power supply interconnect is routed only on the front side of the substrate, then device complexity is reduced, but write operation performance deteriorates due to insufficient voltage level control
Solution Approach 1:
The patent applies dimensionality change by routing power supply interconnects through multiple dimensions: front-side metal layers (M0, M1, M2), back-side metal layers (BM0, BM1), and vertical vias (M0 via, M1 via, M2 via, BM0 via, BM1 via). This multi-dimensional routing enables precise control of voltage levels at memory cells by creating controlled resistance paths without increasing front-side complexity, thereby improving write operation speed while maintaining manageable device complexity.
2Productivity
If additional write-assist circuits are added to improve write operation performance, then write speed improves, but device complexity and overhead increase
Solution Approach 1:
The patent implements self-service by using the power supply interconnect structure itself to provide write assistance. The multi-layer front and back-side routing creates inherent resistance that automatically generates the required voltage drop during write operations, eliminating the need for external write-assist circuits. The interconnect structure serves its own function of voltage level control, improving write speed without adding circuit complexity.
3Productivity
If interconnect resistance is increased to lower power supply voltage level at memory cells, then write operation performance improves, but voltage drop increases
Solution Approach 1:
The patent applies local quality by creating spatially varying resistance distribution through the multi-layer interconnect structure. Different regions of the substrate receive appropriately tailored voltage levels through selectively routed front-side and back-side metal layers. The resistance is locally optimized in specific interconnect paths to achieve the desired voltage drop only where needed for write operations, rather than uniformly across the entire device, thus improving write efficiency while minimizing overall energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the transition time between logic states, improving write operation efficiency and reducing complexity, while maintaining signal integrity and noise margins.
Implementation Method 1
a back side metal via electrically connected to a back surface of the substrate and to the back side metal line, where the back surface is opposite to the front surface of the substrate
Data Source
AI summary
The present disclosure describes a structure with front and back side power supply interconnects. The structure includes a transistor structure disposed in a substrate, where the transistor structure includes a source/drain (S/D) region. The structure also includes a front side power supply line above a top surface of the substrate, wherein the front side power supply line is electrically connected to a power supply metal line. The structure further includes a back side power supply line below a bottom surface of the substrate. A front side metal via electrically connects the front side power supply line to a front surface of the S/D region. A back side metal via electrically connects the back side power supply line to a back surface of the S/D region.