Backside Power Semiconductor Package With Stacked Chip Vias
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Solution Overview
Problem
Conventional semiconductor devices with backside power distribution networks are limited in reducing size and power consumption while maintaining performance, as they are typically configured at the monolithic chip level, leading to inefficiencies in power and signal transfer.
Innovation Solution
A semiconductor package is designed with a first chip featuring a fine wiring structure and backside power distribution network, bonded to a second chip with a larger through via and thicker substrate, and optionally a third chip for heat dissipation, using hybrid bonding or bump bonding to minimize power and signal path resistance and increase structural stability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a monolithic chip structure with backside power distribution network is used, then the device can be compact, but power consumption cannot be effectively reduced and performance is limited
Solution Approach 1:
The semiconductor device is divided into multiple separate chips (first chip with fine wiring and second chip with coarse wiring) that are bonded together. This segmentation allows each chip to be optimized independently - the first chip can have a backside power distribution network for compactness while the second chip provides efficient power transfer pathways, resolving the contradiction between compact structure and power consumption reduction.
2Area of stationary object
If finer wiring structure is used to reduce size, then the device footprint is reduced, but power and signal transfer efficiency deteriorates due to higher resistance
Solution Approach 1:
Different regions of the multi-chip structure have different wiring characteristics - the first chip has fine wiring for compactness while the second chip has thicker through-vias and coarser wiring for lower resistance power transfer. This local differentiation allows the system to achieve both small footprint and efficient power transfer by matching wiring characteristics to functional requirements in different locations.
Solution Approach 2:
The solution moves from a two-dimensional planar wiring problem to a three-dimensional vertical stacking problem. By bonding multiple chips vertically, the system achieves fine wiring area efficiency in the horizontal plane while compensating for resistance losses through the vertical dimension with thicker via structures and optimized inter-chip connections.
3Productivity
If through via size is reduced to increase integration density, then more vias can be packed, but structural stability and current carrying capacity worsen
Solution Approach 1:
The via structure is segmented across multiple chips - the first chip contains smaller through-vias for high integration density while the second chip contains larger through-vias for structural stability and current carrying capacity. This segmentation of via functions across chips allows the system to achieve both high density and structural integrity that would be impossible in a single monolithic chip.
Data Source
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AI summary
A semiconductor package includes a first chip and a second chip bonded to and electrically connected to a front surface of the first chip. The first chip includes a first semiconductor substrate including a first through via, a semiconductor element positioned on a front surface of the first semiconductor substrate, and a back side wiring layer including a back side power wiring positioned on a rear surface of the first semiconductor substrate and electrically connected to the semiconductor element unit. The second chip includes a second through via having a size greater than a size of the first through via.