Backside Power Wiring for Standard Cells With Lower Voltage Drop
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Solution Overview
Problem
The increasing demand for high integration and reduced power consumption in semiconductor processes leads to challenges in efficiently routing lines and vias in integrated circuits, with parasitic elements affecting performance due to decreased power supply voltage.
Innovation Solution
The integration of a backside wiring layer that supplies power to standard cells, allowing for improved routing efficiency and reduced resistance through buried wiring patterns that overlap and connect directly to transistor source/drain areas, thereby enhancing power distribution and reducing voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the width, distance, and height of lines are reduced to achieve high integration, then the integration density increases, but the parasitic elements of the lines increase
Solution Approach 1:
The patent introduces a backside wiring layer on the opposite surface of the substrate from the standard cells. This spatial separation in the third dimension (depth) allows power and ground lines to be routed on the backside, reducing their length and parasitic effects on the front-side standard cells while maintaining high integration density.
Solution Approach 2:
The patent segments the wiring functions by separating power/ground routing from signal routing. The backside wiring layer is dedicated to power and ground connections, while the front side handles standard cell logic. This segmentation reduces the impact of parasitic elements on signal lines by isolating them from high-current power lines.
2Use of energy by moving object
If the power supply voltage is decreased to reduce power consumption, then power efficiency improves, but the effects of parasitic elements increase
Solution Approach 1:
By routing power and ground lines on the backside wiring layer, the patent reduces the length of these lines that would otherwise traverse the front side. Shorter lines mean lower resistance and inductance, reducing parasitic voltage drops and current spikes that would be more problematic at lower supply voltages.
Solution Approach 2:
The backside wiring layer acts as an intermediary structure that mediates between the power supply and the standard cells. It provides dedicated, optimized power distribution paths that minimize parasitic effects, enabling the circuit to operate reliably at lower voltages.
3Adaptability or versatility
If standard cells are arranged on the front surface only, then the routing paths are limited, but the area efficiency decreases
Solution Approach 1:
The patent utilizes the backside of the substrate as an additional dimension for wiring. This doubles the available routing space without increasing the chip's planar footprint, thereby improving area efficiency while providing abundant routing resources for power and ground connections.
Solution Approach 2:
The backside wiring layer serves multiple functions: it provides power distribution, ground connections, and can potentially host additional logic or memory elements. This multi-functionality increases routing resources without proportionally increasing the occupied area.
Data Source
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AI summary
An integrated circuit includes a plurality of standard cells on a front surface of a substrate and a backside wiring layer on a back surface of the substrate, where the plurality of standard cells include a first standard cell, the first standard cell includes a first P-type transistor and a first N-type transistor, the backside wiring layer includes a first backside wiring pattern configured to receive a first power supply voltage, and a third backside wiring pattern configured to receive a first ground voltage, and the first standard cell at least partially overlaps the first backside wiring pattern, and the third backside wiring pattern.