Backside Power Staple Layout for Compact IC Power Routing
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, necessitating new methodologies or technologies to optimize performance and density.
Innovation Solution
The implementation of a backside power staple architecture, which delivers power from the wafer substrate to the front-side metal routing layer through periodic feedthrough vias, reducing the need for wide power wires on the front side and allowing for more compact cell design and lower voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability limiting further miniaturization beyond 10 nanometer node
Solution Approach 1:
The fabrication process is divided into separate modules: forming mandrels with first dimensions, depositing material layers, and etching to create features with second dimensions. This segmentation allows each step to be optimized independently, achieving precise sub-10nanometer features while maintaining overall process manageability
Solution Approach 2:
Mandrels are formed in advance with controlled dimensions before the final feature creation step. These pre-formed mandrels serve as templates that guide subsequent material deposition and etching, ensuring precise feature dimensions are achieved through a controlled sequence of operations
2Productivity
If feature size is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The feature formation is segmented into multiple controlled steps: mandrel formation, material deposition, and selective etching. This allows density to be increased through systematic feature creation while each step maintains precision through independent parameter control
Solution Approach 2:
The process utilizes changes in material properties and deposition/etching parameters to achieve precise feature dimensions. By controlling deposition thickness, etch selectivity, and mandrel dimensions, sub-10nanometer features are formed with high precision while maintaining high device density
3Reliability
If wide power wires are used on the front side to reduce voltage drop, then power delivery reliability is improved, but area occupied by power network increases reducing functional device space
Solution Approach 1:
The power delivery network is moved from the traditional front-side planar layout to the backside of the substrate. This dimensional relocation allows power wires to be routed in a different spatial plane, reducing their projected area on the front side and enabling more functional devices to be placed there while maintaining reliable power delivery through the substrate thickness dimension
Data Source
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AI summary
Integrated circuit structures having backside power staple are described. In an example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts is extending over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A front-side metal routing layer is extending over one or more of the plurality of gate lines, and over and coupled to one or more of the plurality of trench contacts. A backside metal routing layer is extending beneath the one or more of the plurality of gate lines and the one or more of the plurality of trench contacts, the backside metal routing layer parallel and overlapping with the front-side metal routing layer. A conductive feedthrough structure couples the backside metal routing layer to the front-side metal routing layer.