Backside Power Network Structure for IC Step Difference Control
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Solution Overview
Problem
Integrated circuit devices face challenges in increasing integration density and efficiently forming backside power distribution networks due to step differences between device regions, which can lead to resistance issues and damage during etching processes.
Innovation Solution
A backside power distribution network structure (BSPDNS) is implemented with a dam separating substrate portions and a backside insulating layer extending between device regions, alleviating step differences and reducing resistance by forming backside contacts within the insulating layer, and using a dam to prevent etch material spread.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If elements are formed in a substrate or on a backside of the substrate to increase integration density, then integration density is improved, but step differences between device regions are created causing resistance issues and etching damage
Solution Approach 1:
The patent implements a backside power distribution network structure that moves the power distribution function to the backside of the substrate, creating a separate dimensional plane for power delivery. This separates the power distribution layer from the device regions, eliminating step difference issues while maintaining high integration density on the front side.
Solution Approach 2:
The patent introduces a backside insulating layer as an intermediary between the backside power distribution network and the device regions. This insulating layer with varying thickness acts as a mediator that fills step differences and provides a planar surface, preventing etching damage and reducing resistance while allowing both high integration density and reliable device operation.
2Ease of manufacture
If a backside power distribution network is formed without addressing step differences, then device fabrication is simplified, but etch material spreads to damaged regions causing device failure
Solution Approach 1:
The backside insulating layer serves as a protective intermediary between the etching process and the device regions. By placing this insulating layer over the backside power distribution network, the patent prevents etch material from directly contacting and damaging the device regions, while still allowing the fabrication process to proceed with relative simplicity.
Solution Approach 2:
The patent applies the backside insulating layer before the etching process to cushion and protect the device regions from potential etch material damage. This preventive measure is implemented in advance, ensuring that even if etch material spreads, it will not directly damage the sensitive device regions underneath.
3Reliability
If substrate portions are removed to form backside contacts, then resistance is reduced, but step differences increase causing manufacturing complexity
Solution Approach 1:
The patent applies local quality by varying the thickness of the backside insulating layer in different regions. The insulating layer is thicker in areas where substrate removal has created deeper step differences, and thinner in areas with minimal step differences. This localized thickness variation compensates for the step differences created by selective substrate removal, maintaining a relatively planar surface that simplifies subsequent manufacturing steps while preserving the low-resistance backside contacts.
Data Source
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AI summary
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices include a backside power distribution network structure (BSPDNS), a logic device region (101) and a passive device region (102) on the BSPDNS, a backside insulating layer (114) including a first portion extending between the BSPDNS and the logic device region and a second portion extending between the BSPDNS and the passive device region, the passive device region including a semiconductor layer (118) that is in the backside insulating layer, and a dam (130) separating the first portion of the backside insulating layer from the semiconductor layer of the passive device region.