Backside Power Tap Cell Layout for Stable Multi-Row Power Rails
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability and multi-functionality due to complex and highly integrated structures, which require efficient power delivery networks that are not adequately addressed by existing power rail configurations.
Innovation Solution
The semiconductor device incorporates a power tap cell extending across multiple rows with strategically placed power rails and power through vias, forming a power delivery network that provides voltage to power rails, enhancing power distribution and reducing area occupancy by optimizing power tap cell height and placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are extended across multiple rows with power through vias, then power delivery stability is improved, but device complexity increases
Solution Approach 1:
The power delivery network is segmented into multiple power rails (first power rail, second power rail) spaced apart in the second direction, with each rail served by dedicated power through vias. This segmentation allows independent optimization of each power rail's connection to the power delivery network, improving overall power delivery stability while distributing the structural complexity across modular components.
Solution Approach 2:
Power rails are extended into the third dimension by penetrating the substrate through power through vias, transitioning from a two-dimensional surface layout to a three-dimensional vertical structure. This dimensional change enables direct vertical connections between the power delivery network and power rails, enhancing power delivery stability without increasing the horizontal footprint of the power tap cell.
2Area of moving object
If power tap cell height is optimized to reduce area occupancy, then area efficiency is improved, but power distribution effectiveness may worsen
Solution Approach 1:
The power tap cell utilizes vertical penetration through the substrate via power through vias to establish power connections, transitioning from horizontal area expansion to vertical depth utilization. This allows the power tap cell to maintain a compact horizontal footprint while achieving effective power distribution through three-dimensional vertical connections between the power delivery network and power rails.
Solution Approach 2:
The power tap cell is segmented into distinct functional components (power rails, power through vias, expansion parts) that can be independently optimized. The power rails are spaced apart in the second direction, allowing each rail to be efficiently connected to the power delivery network through dedicated vias, thereby reducing overall cell area while maintaining effective power distribution to multiple rails simultaneously.
Data Source
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AI summary
A semiconductor device is provided. The semiconductor device includes a substrate including a first side and a second side that are opposite to each other, a power tap cell in a first row, a second row adjacent to the first row, and a third row adjacent to the second row, on the first side of the substrate, a first power rail and a second power rail on the power tap cell, that extend in a first direction and are spaced apart from each other in a second direction, and a power delivery network on the second side of the substrate. The power tap cell includes a first power through via that penetrates the substrate and extends from the power delivery network to the first power rail, and a second power through via that penetrates the substrate and extends from the power delivery network to the second power rail.