Backside Power Delivery Isolation with Trench Nitridation
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Solution Overview
Problem
Backside power delivery in semiconductor chips poses challenges in patterning electrical contact features isolated from one another within tight spaces without impacting front-side transistor performance.
Innovation Solution
A method involving substrate trench etching, nitridation of inner surfaces, and dielectric filling to form a nitride layer within the trench, protecting extension regions and gate stacks on the front side of the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If backside power delivery is implemented, then power delivery efficiency is improved and interconnect resource sharing is reduced, but patterning electrical contact features in tight spaces becomes more difficult and transistor performance may be impacted
Solution Approach 1:
A nitride layer is deposited on the inner surface of the trench before the trench is filled with dielectric material. This preliminary formation of the nitride layer protects the substrate surface during subsequent processing steps, enabling easier patterning of electrical contact features while maintaining power delivery efficiency.
Solution Approach 2:
A nitride layer is formed as an intermediary protective layer on the trench inner surface. This intermediate layer prevents direct exposure of the substrate to harsh processing conditions during dielectric filling and subsequent patterning operations, thereby facilitating manufacturing in tight spaces without compromising transistor performance.
2Ease of manufacture
If backside power delivery is implemented, then cost savings are achieved by eliminating power delivery tracks, but electrical contact features must be patterned within tight spaces
Solution Approach 1:
The nitride layer is deposited on the trench inner surface before dielectric filling, creating a protective barrier that enables precise patterning of electrical contact features in tight spaces. This preliminary protection allows cost-effective backside power delivery implementation without sacrificing patterning capability.
Solution Approach 2:
A thin nitride film is formed on the trench inner surface, providing flexible protection that conforms to the trench geometry. This thin film enables patterning operations in constrained spaces while maintaining the cost benefits of backside power delivery by eliminating the need for additional power delivery tracks.
3Reliability
If a trench is etched deep into the substrate, then isolation effectiveness is improved, but the substrate below the trench bottom may be damaged
Solution Approach 1:
The nitride layer is deposited on the trench inner surface before dielectric filling and subsequent processing. This preliminary protective layer prevents damage to the substrate regions below the trench bottom during harsh processing steps, achieving both effective isolation and substrate protection.
Solution Approach 2:
The nitride layer serves as a cushioning protective layer on the trench inner surface, absorbing or mitigating harmful effects from subsequent processing operations. This beforehand protection ensures that deep trenches provide effective isolation without causing substrate damage below the trench bottom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective backside power delivery while safeguarding the integrity of extension regions and gate stacks, facilitating optimal metal layer fabrication and reducing interconnect resource sharing.
Implementation Method 1
performing a nitridation process to nitride an inner surface of the trench to form a nitride layer at the inner surface
Data Source
AI summary
A method of backside processing of a transistor structure includes performing a substrate trench etch process to form a trench within a substrate and leave a portion of the substrate below a bottom of the trench un-etched, wherein the trench is aligned with a gate of the transistor structure, performing a nitridation process to nitride an inner surface of the trench to form a nitride layer at the inner surface, and after forming the nitride layer, performing a dielectric fill process to form a dielectric layer within the trench.