Backside Power-Ground TSV Layout With Maximum Decoupling Capacitance
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges with resistance, capacitance, and power consumption issues due to the use of conductive interconnects on the wafer frontside for power and signal routing, particularly when power demand is high, and introducing power signal routing on the wafer backside leads to interference with backside circuit elements and processing challenges with through silicon via (TSV) interconnects.
Innovation Solution
The integration of selective backside power and ground distribution conductors with through silicon via (TSV) structures and decoupling capacitors, formed after FEOL and BEOL processing, to maximize power and ground distribution while providing EMI shielding, by etching TSV openings, lining them with dielectric layers, and filling them with conductive materials to make direct electrical connections with decoupling capacitor plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conductive interconnects on the wafer frontside are used for power and signal routing, then signal delivery is achieved, but resistance, capacitance, and power consumption issues arise when power demand is high
Solution Approach 1:
The patent moves power delivery routing from the traditional wafer frontside (2D plane) to the wafer backside, utilizing the third dimension (depth/substrate thickness) to create dedicated power and ground paths. This spatial separation allows power delivery to occur independently from signal routing, reducing the harmful effects of resistance and capacitance in the interconnect layers while maintaining effective power distribution to high-power devices.
Solution Approach 2:
The patent segments power delivery and signal routing into separate physical paths: power and ground connections are routed through the wafer backside using TSV structures, while signal routing remains on the frontside interconnect layers. This segmentation eliminates the interference between power and signal paths, reducing capacitive coupling and allowing each system to be optimized independently for its specific function.
2Power
If power signal routing is introduced on the wafer backside, then power delivery is improved, but interference with backside circuit elements occurs
Solution Approach 1:
The patent applies local quality by creating spatially differentiated zones on the wafer backside: dedicated power and ground distribution regions use TSV structures for high-current paths, while signal-processing or sensitive circuit elements remain on the frontside or in protected backside regions. This localized functional separation ensures that power routing does not interfere with sensitive circuit operations while maintaining effective power delivery to required locations.
Solution Approach 2:
The patent uses through-silicon via (TSV) structures as intermediary elements that provide isolated conductive paths through the substrate. These TSVs act as controlled mediators between frontside power pads and backside distribution networks, allowing power delivery while maintaining electrical isolation from other backside circuit elements through proper dielectric lining and selective conductivity.
3Reliability
If through silicon via (TSV) interconnects structures are created, then direct electrical connection is achieved, but processing challenges arise
Solution Approach 1:
The patent employs preliminary action by forming the TSV structures, dielectric linings, and conductive fills during the back-end-of-line (BEOL) fabrication process, before final device assembly and testing. This advance preparation ensures that power and ground connections are established early, allowing subsequent processing steps to build upon this reliable foundation without requiring complex post-processing or repair operations.
Solution Approach 2:
The patent utilizes parameter changes in the fabrication process, such as controlling the conductivity, dimensions, and material composition of TSV structures, to optimize both electrical performance and manufacturability. By adjusting parameters like TSV diameter, dielectric thickness, and conductive fill material properties, the process achieves reliable electrical connections while remaining compatible with existing semiconductor manufacturing capabilities.
4Object-affected harmful factors
If decoupling capacitors are placed on the wafer backside, then EMI shielding is improved, but area for capacitor placement is limited
Solution Approach 1:
The patent utilizes the wafer backside as an additional dimensional space for placing decoupling capacitors, effectively doubling the available area for capacitor placement compared to frontside-only designs. This three-dimensional utilization of wafer space allows large-area capacitor arrays to be positioned close to high-power devices while maintaining effective EMI shielding without consuming valuable frontside circuit area.
Data Source
AI summary
A backside power and ground distribution network is formed on an semiconductor wafer having a decoupling capacitor on a backside of the semiconductor substrate layer by selectively etching a TSV openings through the decoupling capacitor and the backside of the semiconductor substrate layer to contact integrated device connection features and then forming, in the TSV openings, a ground TSV conductor which provides a direct electrical connection between the first capacitor plate and a first integrated device connection feature formed in the semiconductor substrate layer and also forming a power TSV conductor which provides a direct electrical connection between the second capacitor plate and a second integrated device connection feature formed in the semiconductor substrate layer, where the ground TSV conductor is not directly, electrically connected to the second capacitor plate, and where the power TSV conductor is not directly, electrically connected to the first capacitor plate.