Backside Power TSV Layout for Buried Power Rail IR-Drop Control
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Solution Overview
Problem
In semiconductor integrated circuits with buried power rails, the increased resistance value of the power delivery network leads to significant power supply voltage drops and noise issues, particularly when power is supplied from a lower chip to an upper chip in stacked configurations.
Innovation Solution
The semiconductor integrated circuit device employs a configuration where the first power is supplied to a buried power rail via a smaller first through electrode from the back face of the first semiconductor chip, while the second power is supplied to a power line in an upper layer via a larger second through electrode, thereby reducing power supply noise and voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power is supplied to the buried interconnect layer from the backside via TSVs, then the power delivery network can supply power to the semiconductor integrated circuit, but the resistance value of the power delivery network increases, causing increased power supply voltage drop
Solution Approach 1:
The patent segments the power delivery network into two independent paths: one for first power supply to the buried power rail and another for second power supply to the upper power line. This segmentation allows each path to be optimized independently, with the second path using a larger TSV to reduce resistance and voltage drop for high-current applications.
Solution Approach 2:
The patent introduces a vertical dimension to the power delivery network by forming TSVs that extend from the backside surface through the substrate to different interconnect layers. This three-dimensional power delivery approach allows power to be supplied from the backside, enabling better thermal management and reduced IR-drop compared to traditional planar power delivery.
2Ease of operation
If power is supplied from the buried interconnect layer to transistors, then the transistors can operate, but power supply noise having occurred in the transistors is liable to travel to an upper interconnect layer
Solution Approach 1:
The patent separates the first power supply network (buried power rail) from the second power supply network (upper power line), preventing noise generated in transistors connected to the first power rail from coupling into the second power line that supplies power to upper interconnect layers.
Solution Approach 2:
The patent introduces separate TSV structures as intermediary elements that provide independent power supply paths. The second TSV with larger cross-sectional area acts as a dedicated low-impedance path for second power, isolating it from noise generated in the first power network.
3Reliability
If the cross-sectional area of the through electrode is increased to reduce resistance, then the power supply voltage drop is reduced, but the manufacturing complexity and device area increase
Solution Approach 1:
The patent applies different cross-sectional areas to different TSVs based on their specific functions: the first TSV has a smaller cross-sectional area suitable for lower current requirements, while the second TSV has a larger cross-sectional area to reduce resistance for high-current second power supply to the upper power line.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces power supply noise and voltage drop in the second power supply, enhancing the performance of stacked semiconductor integrated circuits by minimizing resistance in the power delivery route.
Implementation Method 1
the first buried power rail receives supply of the first power from a back face of the first semiconductor chip via a first through electrode
Implementation Method 2
the first power line receives supply of the second power from the back face of the first semiconductor chip via a second through electrode
Data Source
AI summary
In a semiconductor integrated circuit device, a first semiconductor chip includes: a buried power rail that supplies first power; and a power line that is provided in a layer above the buried power rail and supplies second power. The buried power rail receives supply of the first power from the back face of the first semiconductor chip via a first through electrode, and the power line receives supply of the second power from the back face of the first semiconductor chip via a second through electrode. The cross-sectional area of the second through electrode is greater than the cross-sectional area of the first through electrode.