Backside Power Delivery Circuit With TSV Switching for Smaller Standard Cells
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Solution Overview
Problem
As semiconductor devices shrink in size, minimizing power consumption while maintaining high-speed operations becomes a critical challenge, as existing solutions often require additional circuitry that increases chip area, and existing power management techniques are inefficient in controlling power supply to standard cells.
Innovation Solution
A semiconductor device with a backside power delivery circuit that includes main and local power supply lines connected via through-silicon vias (TSVs), utilizing thin film transistors (TFTs) as switches to control power supply to standard cells, allowing for block-by-block power management and reducing cell height by locating power management components on the backside of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If power management components are located on the front side of the substrate, then power control functionality is achieved, but cell height increases and chip area expands
Solution Approach 1:
The patent moves power management components from the front side (2D plane) to the back side of the substrate, utilizing the third dimension (depth/thickness) to resolve the contradiction. By placing TFT switches and power supply lines on the back side, the front side cell height is reduced while maintaining full power control functionality through vertical interconnects (via holes) that pass through the substrate.
2Adaptability or versatility
If additional circuitry is added for power management, then power control capability is improved, but chip area increases
Solution Approach 1:
The patent utilizes the vertical dimension by placing power management circuitry on the back side of the substrate and using via holes to connect to the front side. This three-dimensional arrangement allows block-by-block power control capability without increasing the planar chip area, as the additional components are stacked vertically rather than laid out horizontally.
3Area of stationary object
If cell height is reduced to minimize device size, then chip area is minimized, but power management becomes more difficult
Solution Approach 1:
By moving power management components to the back side and using vertical via connections, the patent enables reduced front-side cell height while maintaining simplified power management. The separation of power control components from the standard cell area reduces interference and simplifies front-side design, even though it adds back-side processing steps.
Solution Approach 2:
The patent implements block-by-block power control by dividing the chip into multiple power domains, each controlled by independent TFT switches on the back side. This segmentation allows selective power supply to different functional blocks, reducing overall power consumption and simplifying power management for each individual block.
4Area of stationary object
If power supply lines are densely packed to reduce chip area, then area is minimized, but power delivery efficiency decreases
Solution Approach 1:
The patent places wide power supply lines on the back side of the substrate, where they can be routed independently of the dense front-side logic circuitry. This vertical separation allows for wider, lower-resistance power lines that improve power delivery efficiency without consuming additional planar area, as the back-side power lines are viewed as cross-sections through the substrate thickness.
Data Source
AI summary
A semiconductor device includes a substrate, a main circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface of the substrate. The backside power delivery circuit includes a first main power supply wiring for supplying a first voltage, a second main power supply wiring for supplying a second voltage, a first local power supply wiring, and a first switch coupled to the first main power supply wiring and the first local power supply wiring. The first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in a first back side insulating layer disposed over the back surface of the substrate. The first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage.