Backside Power Network With Frontside TSVs for 3D IC IR Drop
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional integrated circuits (3D ICs) experience increased IR drops due to electrical resistances in power grid structures, leading to higher power consumption and degraded device performance as more layers are stacked, which limits the efficiency of power delivery and occupies valuable routing space for signal lines.
Innovation Solution
Implementing a backside power distribution network and frontside deep through silicon vias to reduce IR drops by directly transmitting power from the power source to the device layers, while also increasing routing space for signal lines within the interlayer dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more layers are stacked in 3D IC systems, then chip density is increased, but IR drops increase leading to higher power consumption
Solution Approach 1:
The patent implements a backside power distribution network that delivers power through the substrate thickness dimension, rather than relying solely on planar power grids at the top surface. This vertical power delivery path reduces the horizontal current path length and associated IR drops, enabling higher chip density without proportionally increasing power consumption.
Solution Approach 2:
Through-silicon vias (TSVs) are introduced as intermediary conductive structures that penetrate the substrate to provide direct vertical electrical connections between the backside power distribution network and frontside device layers. These TSVs serve as mediators that efficiently transport power through the substrate thickness, minimizing voltage drops and enabling dense 3D stacking.
2Quantity of substance
If more layers are stacked in 3D IC systems, then chip density is increased, but device performance degrades due to increased IR drops
Solution Approach 1:
By transitioning from a two-dimensional planar power distribution to a three-dimensional architecture with backside power delivery through the substrate, the patent reduces the effective current path length. This dimensional change minimizes IR drops that would otherwise degrade device performance in densely stacked 3D IC systems.
Solution Approach 2:
Through-silicon vias act as intermediary conductive pathways that directly connect the backside power network to frontside device layers, providing low-resistance vertical power delivery. This intermediary structure ensures stable power supply to devices across multiple stacked layers, maintaining device performance despite increased chip density.
3Area of stationary object
If conventional power distribution is used, then routing space is occupied by power grid structures, but power delivery efficiency is reduced
Solution Approach 1:
The patent relocates the power distribution network from the planar top surface to the backside of the substrate, utilizing the substrate thickness dimension for vertical power delivery. This releases valuable planar routing space on the frontside while maintaining efficient power delivery through the vertical dimension via TSVs.
Data Source
AI summary
The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.