Backside Power Via Isolation in Gate Cut Regions
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Solution Overview
Problem
The challenge in semiconductor device fabrication is the potential for electrical shorting between power vias and metal contacts due to congestion in lower BEOL wirings, particularly when power supply wires are moved to the backside of the wafer, leading to increased congestion and shorting risks.
Innovation Solution
The implementation of a semiconductor device with a dielectric liner separating power vias from source/drain epitaxial regions, combined with a backside power rail and distribution network, and the formation of self-aligned power vias through selective etching of dielectric cores, ensuring electrical isolation and reduced congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power supply wires are moved to the backside of the wafer to reduce lower BEOL wiring congestion, then wiring space for signal and power supply becomes wider, but the potential for electrical shorting between power vias and metal contacts increases
Solution Approach 1:
The gate cut region is segmented into multiple functional zones: a first region containing the nanosheet channel and gate stack, a second region containing the source/drain regions, and a third region (power via region) containing the power via. This spatial segmentation isolates the power via from direct contact with metal contacts, reducing shorting risk while maintaining wiring efficiency.
Solution Approach 2:
A dielectric material is introduced as an intermediary substance filling the power via region and surrounding the power via. This dielectric intermediary provides electrical isolation between the power via and adjacent metal contacts, preventing electrical shorting while allowing the power via to maintain its electrical connection through the backside power rail.
2Productivity
If the lower BEOL wirings are congested due to reduced device scale, then space for signal routing and power supply becomes smaller, but moving power supply wires to backside increases shorting potential
Solution Approach 1:
The power distribution architecture transitions from a planar configuration to a three-dimensional structure by moving power supply wires to the backside of the wafer and creating vertical power vias through the substrate. This dimensional change alleviates lower BEOL wiring congestion and enables higher device density while the dielectric isolation in the gate cut region mitigates shorting risks.
Solution Approach 2:
The dielectric material serves as an intermediary isolation layer within the gate cut region, separating the power via from metal contacts. This intermediary structure enables the backside power rail architecture to achieve high device density without compromising reliability from electrical shorting.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.