Backside Power Via Layout for SRAM Source/Drain Contacts
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Solution Overview
Problem
The challenge in forming backside power vias for SRAM devices is that as the critical dimensions of the source/drain regions decrease, there is a risk of missing or not punching through these regions, leading to open circuits and limited process windows.
Innovation Solution
The proposed solution involves forming backside vias that land on the source/drain contacts rather than the source/drain features themselves, allowing the vias to be formed larger than the critical dimensions of the active region, thereby avoiding process window concerns and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside power vias are formed by etching trenches through source/drain regions, then electrical connection to back side power lines is achieved, but risk of open circuit increases and process window is limited when critical dimensions become small
Solution Approach 1:
The patent introduces an intermediary structure (the via trench formation process using mandrels and spacers) between the etching step and the final via formation. This intermediary approach allows for better control of the etching process by defining the trench boundaries beforehand, reducing the risk of missing the source/drain regions and improving overall manufacturing precision.
2Reliability
If backside vias are formed to land on source/drain features, then electrical connection is established, but via size is limited by critical dimensions of active region
Solution Approach 1:
The patent transitions from a two-dimensional via formation approach to a three-dimensional approach by forming vias that extend through multiple layers and land on the top surface of source/drain features rather than through them. This dimensional change allows for larger via areas without being constrained by the critical dimensions of the active region, while still achieving reliable electrical connection.
3Productivity
If source/drain region critical dimensions are reduced for scaling, then device density increases, but process window for via formation decreases
Solution Approach 1:
The patent segments the via formation process into distinct steps: forming mandrels, depositing spacer material, pattern transfer, and etching. This segmentation allows each step to be optimized independently, enabling via formation even when source/drain region critical dimensions are reduced for scaling, thereby maintaining ease of manufacture while increasing device density.
Data Source
AI summary
A semiconductor structure includes a first source/drain (S/D) epitaxial feature, a second S/D epitaxial feature adjacent to the first S/D epitaxial feature, an insulating structure between the first and the second S/D epitaxial features, and a shared S/D contact over top surfaces of the first and the second S/D epitaxial features. A center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature. The center portion is directly above the insulating structure. The semiconductor structure further includes a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.