Backside Power Rail Via Profile for Low-Resistance 3D IC Routing
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Solution Overview
Problem
Conventional power distribution networks in 3D monolithic IC designs occupy significant area, limiting integration density and causing challenges in forming narrow electrical connections to backside power delivery networks, which increase resistance and affect device performance.
Innovation Solution
The semiconductor structure incorporates a middle-of-line contact and a backside power rail with a contact via that has a unique tapered profile, comprising a positive tapered upper portion and a negative tapered lower portion, allowing for efficient power transmission while minimizing the risk of shorting between adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power distribution networks are used with parallel power busses in BEOL, then power delivery is achieved, but area occupancy increases significantly limiting integration density
Solution Approach 1:
The patent moves the power delivery network from the conventional planar BEOL layers to the backside of the substrate, utilizing the third dimension (vertical stacking) to resolve the area occupancy issue. By forming power rails and contact vias on the backside, the design achieves efficient power distribution without consuming valuable frontside layout area, thereby improving integration density while maintaining reliable power delivery.
2Area of stationary object
If narrow electrical connections are formed to backside power delivery networks, then area occupancy is reduced, but contact resistance increases affecting device performance
Solution Approach 1:
The patent applies different taper profiles to different portions of the contact via structure. The upper portion has a first tapered profile while the lower portion has a second tapered profile, with each optimized for its specific location. This local differentiation allows the via to achieve low resistance at the critical backside interface while maintaining narrow dimensions in the upper regions, thus resolving the contradiction between area efficiency and contact resistance.
Solution Approach 2:
The patent changes the geometric parameters of the contact via by implementing asymmetric taper profiles. The via transitions from a uniform cylindrical shape to a structured form with varying cross-sectional dimensions along its length. This parameter modification enables the via to optimize electrical conductivity at the backside power rail interface while maintaining space efficiency in the upper portions, effectively addressing both area occupancy and contact resistance concerns.
3Ease of manufacture
If contact vias with uniform profiles are used, then manufacturing is simplified, but shorting risk increases in narrow connections
Solution Approach 1:
The patent implements different tapered profiles for different portions of the contact via. The upper portion features a first taper designed to minimize shorting risk in narrow regions, while the lower portion has a second taper optimized for electrical contact. This localized differentiation maintains manufacturing feasibility through established etching processes while significantly reducing shorting risk in the critical narrow upper sections where adjacent cell isolation is most challenging.
Data Source
AI summary
A semiconductor structure including a middle-of-line contact, a backside power rail, and a contact via extending between the middle-of-line contact and the backside power rail, wherein the contact via comprises a first portion having a negative tapered profile and a second portion having a positive tapered profile.