Backside Power Via Segmentation to Reduce RIE Depth

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Solution Overview

Problem

The integration of power delivery networks in the back end of line (BEOL) structure of semiconductor devices has become challenging due to increasing device densities, leading to difficulties in backside power delivery and increased risks of resistance, parasitic capacitance, and via-to-gate shorts.

Innovation Solution

A method for building backside power vias over two stages, pre- and post-wafer flip, using a bi-layer liner in the gate cut, which reduces the required RIE depth and minimizes resistance, parasitic capacitance, and backside via-to-gate short risk.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If backside power vias are formed using conventional single-stage processes, then the via structure can be completed, but the RIE depth becomes excessive causing high resistance, parasitic capacitance, and via-to-gate short risks

Engineering Contradiction:

Improvevia-to-gate short riskVSAvoidRIE depth

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The backside power via is divided into two separate formation stages: a first portion formed pre-wafer flip during BEOL processing, and a second portion formed post-wafer flip. This segmentation reduces the required RIE depth at each stage, thereby reducing resistance, parasitic capacitance, and via-to-gate short risks while maintaining complete via functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first portion of the backside power via is formed before wafer flip during the BEOL process, establishing a foundation that simplifies the subsequent second stage formation after wafer flip. This preliminary action reduces the complexity and depth requirements of the final via structure.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If device density is scaled up, then more active devices can be placed on the chip, but the PDN integration becomes more challenging with increased resistance and parasitic capacitance

Engineering Contradiction:

Improvedevice densityVSAvoidPDN performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

Instead of forming the complete power delivery network on the front side of the wafer during BEOL, the invention inverts the approach by forming portions of the power vias on the backside of the wafer. This inversion allows the PDN to be integrated without adding to the front-side congestion, enabling higher device density while maintaining PDN performance through reduced via depth and resistance.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20250048715A1Backside power via

Publication Date: 2025.02.06 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Embodiments of the present invention are directed to processing methods and resulting structures for providing power vias through a wafer backside. In a non-limiting embodiment of the invention, a gate and a source or drain (S/D) region are formed on a substrate. A bi-layer liner is formed in a gate cut of the gate. The bi-layer liner includes a first liner on sidewalls of the gate cut and a second liner between the first liner. A top portion of the second liner is replaced with a first portion of a backside power via and the semiconductor device is flipped. A bottom portion of the second liner is replaced with a second portion of the backside power via.