Backside Power Via Stack for Scaled MOSFET Reliability
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate, leading to limitations in performance and integration, necessitating improved methods for forming semiconductor devices with enhanced electrical characteristics and reliability.
Innovation Solution
The semiconductor device design includes a substrate with active and source/drain patterns, metal layers for power interconnection, through-vias penetrating the substrate, and a power delivery network layer, where the through-vias consist of a first metal pattern with higher density and resistivity than a second metal pattern, optimized for improved electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to reduce device size, then integration density increases, but operating characteristics deteriorate
Solution Approach 1:
The through-via is divided into multiple metal patterns (first metal pattern and second metal pattern) with different properties. The first metal pattern provides mechanical strength and density, while the second metal pattern provides low resistivity, thereby resolving the contradiction between device scaling and operating characteristics maintenance.
Solution Approach 2:
The through-via employs a composite structure combining different metal patterns with complementary properties. This composite approach allows the via to simultaneously achieve the mechanical integrity needed for scaled devices and the electrical performance required for maintaining operating characteristics.
2Ease of manufacture
If through-vias use single metal pattern, then manufacturing is simpler, but electrical characteristics and reliability are insufficient
Solution Approach 1:
Different metal patterns are placed in different regions of the through-via based on local requirements. The first metal pattern is positioned where mechanical strength and density are critical, while the second metal pattern is positioned where low resistivity is paramount, optimizing both manufacturing and performance.
Solution Approach 2:
The solution transitions from a single-metal to a multi-layer metal structure in the vertical dimension. This dimensional approach allows simultaneous optimization of different properties (density, resistivity) by stacking metal patterns with complementary characteristics.
3Reliability
If power delivery network is optimized, then electrical characteristics improve, but device complexity increases
Solution Approach 1:
The power delivery network's through-via is segmented into multiple metal patterns, each optimized for specific functions. This segmentation improves electrical characteristics by reducing resistivity in critical paths while maintaining a structured, manageable complexity through systematic layering.
Data Source
AI summary
A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a first metal layer on the source/drain pattern, the first metal layer comprising a power interconnection line, a through-via electrically connected to the power interconnection line, the through-via vertically extending to penetrate the substrate, a power delivery network layer on a bottom surface of the substrate, and a lower through-via between the power delivery network layer and the through-via. The through-via includes a first metal pattern connected to the lower through-via, and a second metal pattern stacked on the first metal pattern. A density of the first metal pattern is greater than a density of the second metal pattern. A resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.