Backside Power Via Layout for Continuous Transistor Performance Tuning
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in scaling to sub-10 nanometer nodes due to variability and limitations in device performance tuning, particularly lacking a method for continuous parameter modulation of transistor performance.
Innovation Solution
The use of deep trench vias for backside power delivery allows for continuous tuning of device characteristics by varying the distance of the via from the transistor, enabling up to 10% faster performance or 30%-40% lower leakage through strain effects and fixed charge modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing cost and infrastructure compatibility are maintained, but device performance tuning capability and manufacturing precision are limited
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the deep trench via structure separately, then using it as a strain template during subsequent transistor fabrication. This segmentation allows the via to independently provide strain effects without complicating the overall fabrication flow, thereby improving device performance tuning while maintaining process simplicity
Solution Approach 2:
The deep trench via is formed in advance before transistor fabrication, creating a pre-established strain field that will automatically affect the transistor performance during subsequent processing steps. This preliminary action enables performance tuning without requiring additional complex steps during transistor fabrication
2Adaptability or versatility
If digital tuning methods are used, then device performance can be adjusted in discrete steps, but continuous parameter modulation is not achieved
Solution Approach 1:
The invention changes the physical parameter of the via (its distance from the transistor channel) to continuously modulate strain effects. By varying this geometric parameter, continuous adjustment of transistor performance is achieved, transitioning from discrete digital tuning to continuous analog control of device characteristics
3Productivity
If feature size is reduced to increase device density, then capacity increases, but variability in fabrication processes worsens and performance tuning becomes more difficult
Solution Approach 1:
The deep trench via creates localized strain effects precisely where needed in the transistor structure. This local quality enhancement allows individual device tuning without affecting neighboring devices, thereby managing fabrication variability at the device level while maintaining high overall device density
Solution Approach 2:
The deep trench via acts as an intermediary structure that mediates between the substrate and the transistor channel, providing controlled strain effects. This intermediary enables performance tuning without directly modifying the transistor fabrication process, thereby reducing the impact of fabrication variability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a means to continuously adjust transistor performance, overcoming the limitations of existing digital tuning methods and enhancing device efficiency.
Implementation Method 1
enabling up to 10% faster performance or 30%-40% lower leakage through strain effects and fixed charge modulation
Data Source
AI summary
Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate and a transistor over the substrate. In an embodiment, the transistor comprises a source, a gate, and a drain. In an embodiment, the semiconductor device further comprises a first metal layer above the transistor, where the first metal layer comprises, a source metal coupled to the source, a drain metal coupled to the drain, and a gate metal coupled to the gate. In an embodiment, the source metal, the drain metal, and the gate metal are parallel conductive lines. In an embodiment, a backside via passes through the substrate, and a contact metal in the first metal layer is coupled to the backside via. In an embodiment, the contact metal is oriented orthogonal to the source metal.