Backside Power Delivery Network for Lower Voltage Drop

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Solution Overview

Problem

Existing power delivery networks in device dies face challenges in efficiently delivering power to integrated circuits while managing heat dissipation and minimizing voltage drop.

Innovation Solution

A backside power delivery network is implemented with front-side power input, utilizing electrical connectors on the front side of the device die to distribute power to the backside, enhancing heat dissipation and reducing voltage drop through wider power lines on the backside.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If power is delivered through front-side interconnect structures, then power delivery is achieved, but heat dissipation is insufficient and voltage drop increases

Engineering Contradiction:
Improveheat dissipationVSAvoidvoltage drop
Core Design Contradiction:
TemperatureVSLoss of energy

Solution Approach 1:

The patent moves the power delivery network from the front side to the back side of the device die, utilizing the third dimension (depth/thickness) of the device structure. By routing power lines on the back side, the design creates additional spatial freedom, allowing for wider power lines that reduce resistance and voltage drop while improving heat dissipation through better thermal pathways.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Instead of the conventional approach of delivering power through front-side interconnect structures, the patent inverts the approach by implementing power delivery through back-side interconnect structures. This inversion allows the front side to be dedicated primarily to signal routing while the back side handles power distribution, resolving the conflicts between power delivery efficiency, heat management, and signal integrity.

Inventive Principle:
Principle #13The other way round (Inversion)

2Power

If front-side space is used for power routing, then power delivery is achieved, but signal routing space is reduced

Engineering Contradiction:
Improvepower delivery efficiencyVSAvoidsignal routing complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent segments the device die into distinct functional zones: the front side is dedicated to signal routing and active circuitry, while the back side is dedicated to power delivery. This segmentation allows each side to be optimized for its specific function without interfering with the other, reducing overall device complexity while improving power delivery efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By utilizing the back side of the device die for power routing, the patent effectively adds another dimension to the interconnect architecture. This dimensional separation allows simultaneous optimization of both signal routing (on the front) and power delivery (on the back) without compromising either function.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves heat dissipation and reduces voltage drop by routing power to the backside of the device die, freeing up front-side space for signal routing and allowing for wider power lines, thus optimizing power delivery efficiency.

Implementation Method 1

The power (VDD and VSS) is conducted to the backside of the device die

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20250329652A1Backside power scheme with front-side power input
Publication Date: 2025.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250329652A1 patent drawing
  • US20250329652A1 patent drawing
  • US20250329652A1 patent drawing

AI summary

A method includes forming integrated circuit devices comprising a transistor formed at a top surface of a semiconductor substrate of a wafer, forming a front-side interconnect structure over and connecting to the integrated circuit devices, forming an electrical connector over and connecting to the front-side interconnect structure, performing a backside grinding process to thin the semiconductor substrate, and forming a backside interconnect structure on a backside of the integrated circuit devices. The backside interconnect structure includes a power delivery network, and is configured to receive a positive power supply voltage from the electrical connector and redistributes the positive power supply voltage to the integrated circuit devices.