Backside Power Delivery Circuit Layout for Warpage-Balanced Packaging
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Solution Overview
Problem
High performance computing (HPC) systems for electronic devices face challenges in power consumption and heat dissipation, which are exacerbated by the need to minimize electromagnetic interference and accommodate varying voltage and power requirements across multiple dies, ultimately limiting miniaturization efforts.
Innovation Solution
The electronic device incorporates an electronic component with a power delivery circuit disposed on its backside surface, featuring a redistribution structure and reinforcement structures to balance warpage and enhance rigidity, thereby facilitating efficient power transmission and supporting the integration of multiple functions without compromising miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power routing paths are provided over a system board with multiple dies mounted, then power transmission is enabled, but electromagnetic interference between power signals and non-power signals increases and miniaturization is limited
Solution Approach 1:
The patent segments the electronic device into distinct functional layers: an electronic component layer, a power delivery circuit layer, and an I/O signal delivery circuit layer. This vertical segmentation separates power signals from non-power signals, enabling power transmission while minimizing electromagnetic interference through spatial isolation of different signal types.
Solution Approach 2:
The patent transitions from planar power routing on a system board to three-dimensional power delivery through stacked layers. The power delivery circuit is positioned on the backside surface of the electronic component, creating a vertical power transmission path that eliminates electromagnetic interference with co-planar signal routes and enables device miniaturization.
2Reliability
If power is provided through power regulating components over an interconnection structure or interconnection die, then power routing stability is improved, but device size increases and miniaturization is constrained
Solution Approach 1:
The patent merges the power delivery function directly into the electronic component structure by forming the power delivery circuit on the backside surface of the electronic component. This integration eliminates the need for separate interconnection structures or interconnection dies, maintaining power routing stability while reducing overall device volume and enabling miniaturization.
Solution Approach 2:
The power delivery circuit is nested within the electronic component structure, utilizing the backside surface space that would otherwise be unused. This nested configuration provides stable power routing through direct contact with the electronic component while minimizing the external footprint and supporting device miniaturization.
3Adaptability or versatility
If multiple dies are integrated to accommodate varying voltage and power requirements, then functional versatility is improved, but the number of power routing paths increases and miniaturization is limited
Solution Approach 1:
The patent segments different voltage and power requirement zones within the electronic component and provides dedicated power delivery circuit regions for each segment. This segmentation enables multiple dies with varying power requirements to be integrated while maintaining organized, minimal power routing paths through vertical layering rather than horizontal expansion.
Solution Approach 2:
The patent resolves the complexity of multiple power routing paths by transitioning to three-dimensional power delivery. Multiple power delivery circuits are stacked vertically on the backside surface, allowing each die to receive power through dedicated vertical paths rather than requiring complex horizontal routing, thereby supporting functional versatility while enabling miniaturization.
Data Source
AI summary
An electronic device is disclosed. The electronic device includes an electronic component, an input/output (I/O) signal delivery circuit, and a power delivery circuit. The electronic component has a first surface and a second surface opposite to the first surface. The I/O signal delivery circuit is disposed under the first surface of the electronic component. The power delivery circuit is disposed over the second surface of the electronic component and configured to balance a warpage of the electronic device.