Backside Power Wiring Layout for Dense Standard Cell ICs
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Solution Overview
Problem
The increasing demand for high integration and reduced power consumption in semiconductor processes leads to increased parasitic effects in integrated circuits, necessitating efficient routing of lines and vias while minimizing power supply voltage, which existing technologies struggle to address effectively.
Innovation Solution
The integration of a backside wiring layer in integrated circuits that supplies power to standard cells, allowing for reduced routing complexity and improved performance by using multiple backside wiring patterns to distribute power efficiently, with vias connecting these patterns to transistor source/drain areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the width, distance, and height of lines are reduced to achieve high integration, then the integration density is improved, but the parasitic elements of the lines increase
Solution Approach 1:
The patent introduces a backside wiring layer, adding a new dimension (z-axis) to the wiring structure. This allows power supply lines to be routed on the backside of the substrate, separating them from the frontside signal lines and reducing parasitic coupling effects while maintaining high integration density on the frontside.
2Use of energy by moving object
If the power supply voltage is decreased to achieve reduced power consumption, then the power consumption is reduced, but the effects of parasitic elements on the integrated circuit increase
Solution Approach 1:
By routing power supply lines on the backside wiring layer, the patent reduces the loop area and parasitic inductance of power delivery paths. This enables lower power supply voltages to be used effectively, as the reduced parasitic effects prevent excessive voltage drops and ringing that would otherwise limit voltage reduction.
Solution Approach 2:
The backside wiring layer is divided into multiple segmented power supply lines (first backside wiring pattern, second backside wiring pattern, third backside wiring pattern) that can be independently optimized. This segmentation allows for reduced via counts and lower parasitic effects in each segment, enabling effective low-voltage operation.
3Productivity
If multiple backside wiring patterns are used to distribute power efficiently, then the routing resource utilization is improved, but the device complexity increases
Solution Approach 1:
The backside wiring layer patterns serve multiple functions: they provide power supply distribution, act as ground references, and reduce parasitic effects on frontside signal lines. This multi-functionality justifies the increased complexity by delivering multiple benefits from a single structural addition.
Data Source
AI summary
An integrated circuit includes a plurality of standard cells on a front surface of a substrate and a backside wiring layer on a back surface of the substrate, where the plurality of standard cells include a first standard cell, the first standard cell includes a first P-type transistor and a first N-type transistor, the backside wiring layer includes a first backside wiring pattern configured to receive a first power supply voltage, a second backside wiring pattern configured to receive a second power supply voltage, and a third backside wiring pattern configured to receive a ground voltage, and the first standard cell at least partially overlaps the first backside wiring pattern, the second backside wiring pattern, and the third backside wiring pattern.