Back-Side Power Rail Capping for Lower IR Drop and Capacitance

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Solution Overview

Problem

Current semiconductor transistor devices face challenges with complex metal layer routing in the back-end-of-line (BEOL) process as the technology scales beyond 3 nm, leading to increased mask requirements and voltage drop issues due to thin metal wires, which complicates power rail design and increases cell capacitance.

Innovation Solution

The implementation of a semiconductor transistor device with a back-side power rail and recessed source/drain regions, where the power rail is moved from the front side to the back side, reducing metal layer routing complexity, minimizing mask requirements, and utilizing a back-side dielectric cap to reduce cell capacitance and eliminate current leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power rail is placed on the front side with conventional metal layer routing, then device functionality is achieved, but metal layer routing complexity increases and voltage drop occurs due to thin metal wires

Engineering Contradiction:

Improvevoltage drop performanceVSAvoidmetal layer routing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent inverts the conventional power rail placement by moving it from the front side to the back side of the transistor device. This inversion simplifies the metal layer routing architecture and reduces routing complexity in the BEOL process, while also improving voltage drop performance through more efficient power delivery paths.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent utilizes the vertical dimension by placing the power rail on the back side of the device, effectively using the third dimension (depth) to resolve the routing complexity issue. This dimensional change allows for simpler metal layer routing without compromising device functionality.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If technology scales down beyond 3 nm, then transistor density increases, but mask requirements increase and metal wire thickness decreases causing voltage drop

Engineering Contradiction:

Improvetransistor densityVSAvoidvoltage drop performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

By inverting the power rail placement to the back side, the patent enables better power delivery at scaled dimensions, compensating for the voltage drop issues that arise when metal wires become thinner due to scaling.

Inventive Principle:

Principle #13The other way round (Inversion)

3Reliability

If conventional front-side power rail design is used, then device operation is achieved, but cell capacitance increases

Engineering Contradiction:

Improvedevice operationVSAvoidcell capacitance

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The back-side power rail configuration reduces cell capacitance by optimizing the electrical field distribution and reducing parasitic effects, while maintaining full device operational capability.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS11935794B2Method for forming long channel back-side power rail device

Publication Date: 2024.03.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.